8.2.2.18.1 R4, C18, C17

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One advantage of current mode control is the ability to close the loop with only three feedback components, R4, C18, and C17. The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of the LM25118 is as follows:

Equation 46.

The dominant, low frequency pole of the modulator is determined by the load resistance (R_LOAD) and output capacitance (C_OUT). The corner frequency of this pole is:

Equation 47.

For this example, R_LOAD = 4 Ω, D_MAX = 0.705, and C_OUT = 454 µF, therefore:

Additionally, there is a right-half plane (RHP) zero associated with the modulator. The frequency of the RHP zero is:

Equation 50.

The output capacitor ESR produces a zero given by:

Equation 52.

The RHP zero complicates compensation. The best design approach is to reduce the loop gain to cross zero at about 25% of the calculated RHP zero frequency. The Type ll error amplifier compensation provided by R4, C18, and C17 places one pole at the origin for high DC gain. The second pole should be placed close to the RHP zero. The error amplifier zero (Equation 54) should be placed near the dominate modulator pole. This is a good starting point for compensation.

Components R4 and C18 configure the error amplifier as a Type II configuration which has a DC pole and a zero at

Equation 54.

C17 introduces an additional pole used to cancel high frequency switching noise. The error amplifier zero cancels the modulator pole leaving a single pose response at the crossover frequency of the loop gain if the crossover frequency is much lower than the right half plane zero frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 2.0 kHz was selected (about 25% of the right-half-plane zero frequency). The error amplifier zero (fz) should be selected at a frequency near that of the modulator pole and much less than the target crossover frequency. This constrains the product of R4 and C18 for a desired compensation network zero to be less than 2 kHz. Increasing R4, while proportionally decreasing C18 increases the error amp gain. Conversely, decreasing R4 while proportionally increasing C18 decreases the error amp gain. For the design example C18 was selected for 100 nF and R4 was selected to be 10 kΩ. These values set the compensation network zero at 159 Hz. The overall loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given. Step load transient tests can be performed to verify acceptable performance. The step load goal is minimal overshoot with a damped response.

Please see the plots shown in Figure 21 through Figure 26 which illustrate the gain and phase diagrams of the design example.