ZHCSLO7B December   2020  – January 2023 LM25149-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings 
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Active EMI Filter
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN)
      2. 8.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 8.3.3  Precision Enable (EN)
      4. 8.3.4  Power-Good Monitor (PG)
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Active EMI Filter
      7. 8.3.7  Dual Random Spread Spectrum (DRSS)
      8. 8.3.8  Soft Start
      9. 8.3.9  Output Voltage Setpoint (FB)
      10. 8.3.10 Minimum Controllable On Time
      11. 8.3.11 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      12. 8.3.12 Slope Compensation
      13. 8.3.13 Inductor Current Sense (ISNS+, VOUT)
        1. 8.3.13.1 Shunt Current Sensing
        2. 8.3.13.2 Inductor DCR Current Sensing
      14. 8.3.14 Hiccup Mode Current Limiting
      15. 8.3.15 High-Side and Low-Side Gate Drivers (HO, LO)
      16. 8.3.16 Output Configurations (CNFG)
      17. 8.3.17 Single-Output Dual-Phase Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
      3. 8.4.3 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 Power MOSFETs
        5. 9.1.1.5 EMI Filter
        6. 9.1.1.6 Active EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High-Efficiency 2.1-MHz Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Custom Design With Excel Quickstart Tool
          3. 9.2.1.2.3  Buck Inductor
          4. 9.2.1.2.4  Current-Sense Resistance
          5. 9.2.1.2.5  Output Capacitors
          6. 9.2.1.2.6  Input Capacitors
          7. 9.2.1.2.7  Frequency Set Resistor
          8. 9.2.1.2.8  Feedback Resistors
          9. 9.2.1.2.9  Compensation Components
          10. 9.2.1.2.10 Active EMI Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – High Efficiency 440-kHz Synchronous Buck Regulator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Design 3 – Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate-Drive Layout
        3. 9.4.1.3 PWM Controller Layout
        4. 9.4.1.4 Active EMI Layout
        5. 9.4.1.5 Thermal Design and Layout
        6. 9.4.1.6 Ground Plane Design
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

Connect the exposed pad to AGND and PGND on the PCB.
Figure 6-1 24-Pin VQFN RGY Package with Wettable Flanks(Top View)
Table 6-1 Pin Functions
PIN I/O(1) DESCRIPTION
NO. NAME
1 AVSS G Active EMI bias ground connection
2 INJ O Active EMI injection output
3 CNFG 1 Connect a resistor to ground to set primary/secondary, spread spectrum enable/disable, or interleaved operation. After start-up, use CNFG to enable AEF.
4 RT I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100 kHz and 2.2 MHz.
5 EXTCOMP O The output of the transconductance error amplifier. If used, connect the compensation network from EXTCOMP to AGND.
6 FB I Connect FB to VDDA to set the output voltage to 3.3 V. Connect FB using a 24.9 kΩ or 49.9 kΩ to VDDA to set the output voltage to 5 V or 12 V, respectively. Install a resistor divider from VOUT to AGND to set the output voltage setpoint between 0.8 V and 36 V. The regulation voltage at FB is 0.8 V.
7 AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits.
8 VDDA O Internal analog bias regulator. Connect a ceramic decoupling capacitor from VDDA to AGND.
9 VCC P VCC bias supply pin. Connect ceramic capacitors between VCC and PGND.
10 PGND G Power ground connection pin for low-side power MOSEFT gate driver
11 LO O Low-side power MOSFET gate driver output
12 VIN P Supply voltage input source for the VCC regulators
13 HO O High-side power MOSFET gate driver output
14 SW P Switching node of the buck regulator and high-side gate driver return. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
15 CBOOT P High-side driver supply for bootstrap gate drive
16 VCCX P Optional input for an external bias supply. If VVCCX > 4.3 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled.
17 PG/SYNCOUT P An open-collector output that goes low if VOUT is outside the specified regulation window. The PG/SYNCOUT pin of the primary controller in dual-phase mode provides a 180° phase-shifted SYNCOUT signal.
18 PFM/SYNC I Connect PFM/SYNC to VDDA to enable diode emulation mode. Connect PFM to GND to operate the LM25149-Q1 in forced PWM (FPWM) mode with continuous conduction at light loads. PFM/SYNC can also be used as a synchronization input to synchronize the internal oscillator to an external clock.
19 EN I An active-high precision input with rising threshold of 1 V and hysteresis current of 10 µA. If the EN voltage is less than 0.5 V, the LM25149-Q1 is in shutdown mode, unless a SYNC signal is present on PFM/SYNC.
20 ISNS+ I Current sense amplifier input. Connect the ISNS+ to the inductor side of the external current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a Kelvin connection.
21 VOUT I Output voltage sense and the current sense amplifier input. Connect VOUT to the output side of the current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used).
22 AEFVDDA P Active EMI bias power. Connect a ceramic capacitor between AEFVDDA and AVSS.
23 SENSE I Active EMI sense input
24 REFAGND G Active EMI reference ground
(1) P = Power, G = Ground, I = Input, O = Output
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