10.1 Layout Guidelines

PCB layout is a critical for good power supply design. There are several paths that conduct high slew-rate currents or voltages that can interact with transformer leakage inductance or parasitic capacitance to generate noise and EMI or degrade the power supply's performance.

1. Bypass the VIN pin to GND with a low-ESR ceramic capacitor, preferably of X7R or X7S dielectric. Place C_IN as close as possible to the LM25180-Q1 VIN and GND pins. Ground return paths for the input capacitor(s) must consist of localized top-side planes that connect to the GND pin and exposed PAD.
2. Minimize the loop area formed by the input capacitor connections and the VIN and GND pins.
3. Locate the transformer close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive e-field or capacitive coupling.
4. Minimize the loop area formed by the diode-Zener clamp circuit connections and the primary winding terminals of the transformer.
5. Minimize the loop area formed by the flyback rectifying diode, output capacitor and the secondary winding terminals of the transformer.
6. Connect adequate copper at the cathode of the flyback diode to prevent overheating during overload or high ambient temperature conditions.
7. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
8. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
9. Have a single-point ground connection to the plane. Route the return connections for the reference resistor, soft-start, and enable components directly to the GND pin. This prevents any switched or load currents from flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic output voltage ripple behavior.
10. Make V_IN+, V_OUT+ and ground bus connections short and wide. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
11. Minimize trace length to the FB pin. Locate the feedback resistor close to the FB pin.
12. Locate components R_SET, R_TC and C_SS as close as possible to their respective pins. Route with minimal trace lengths.
13. Place a capacitor between input and output return connections to route common-mode noise currents directly back to their source.
14. Provide adequate heatsinking for the LM25180-Q1 to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the exposed PAD to the PCB ground plane. If the PCB has multiple copper layers, connect these thermal vias to inner-layer ground planes. The connection to V_OUT+ provides heatsinking for the flyback diode.