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7.1 Absolute Maximum Ratings ⁽¹⁾⁽²⁾

			MIN	MAX	UNIT
Maximum supply voltage, V_IN				45	V
SD/SS pin input voltage⁽³⁾				6	V
Delay pin voltage⁽³⁾				1.5	V
Flag pin voltage			–0.3	45	V
Feedback pin voltage			–0.3	25	V
Output voltage to ground (steady-state)				–1	V
Power dissipation			Internally limited
Lead temperature	KTW package	Vapor phase (60 s)		215	°C
	KTW package	Infrared (10 s)		245
	NDZ package (soldering, 10 s)			260
Maximum junction temperature				150	°C
Storage temperature, T_stg			−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(3) Voltage internally clamped. If clamp voltage is exceeded, limit current to a maximum of 1 mA.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

	MIN	MAX	UNIT
Supply voltage	4.5	40	V
Temperature	–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾			LM2599		UNIT
			KTW (TO-263)	NDZ (TO-220)
			7 PINS	7 PINS
R_θJA	Junction-to-ambient thermal resistance⁽²⁾⁽³⁾	See⁽⁴⁾	—	50	°C/W
		See⁽⁵⁾	50	—
		See⁽⁶⁾	30	—
		See⁽⁷⁾	20	—
R_θJC(top)	Junction-to-case (top) thermal resistance		2	2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) The package thermal impedance is calculated in accordance to JESD 51-7.

(3) Thermal resistances were simulated on a 4-layer, JEDEC board.

(4) Junction to ambient thermal resistance (no external heat sink) for the package mounted TO-220 package mounted vertically, with the leads soldered to a PCB with 1-oz copper area of approximately 1 in².

(5) Junction to ambient thermal resistance with the TO-263 package tab soldered to a single-sided PCB with 0.5 in² of 1-oz copper area.

(6) Junction to ambient thermal resistance with the TO-263 package tab soldered to a single-sided PCB with 2.5 in² of 1-oz copper area.

(7) Junction to ambient thermal resistance with the TO-263 package tab soldered to a double-sided PCB with 3 in² of 1-oz copper area on the LM2599S side of the board, and approximately 16 in² of copper on the other side of the PCB.

7.5 Electrical Characteristics – 3.3-V Version

Specifications are for T_J = 25°C (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN⁽¹⁾	TYP⁽²⁾	MAX ⁽¹⁾	UNIT
SYSTEM PARAMETERS⁽³⁾ (see Figure 43 for test circuit)
V_OUT	Output voltage	4.75 V ≤ V_IN ≤ 40 V, 0.2 A ≤ I_LOAD ≤ 3 A	T_J = 25°C	3.168	3.3	3.432	V
V_OUT	Output voltage	4.75 V ≤ V_IN ≤ 40 V, 0.2 A ≤ I_LOAD ≤ 3 A	–40°C ≤ T_J ≤ 125°C	3.135		3.465	V
η	Efficiency	V_IN = 12 V, I_LOAD = 3 A			73%

(1) All room temperature limits are 100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).