SNVS457D February   2007  – October 2015 LM26400Y

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Overcurrent Protection
      2. 7.3.2 Loop Stability
      3. 7.3.3 Load Step Response
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up and Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 LM26400Y Design Example 1
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LM26400Y Design Example 2
  9. 9 Power Supply Recommendations
    1. 9.1 Low Input Voltage Considerations
    2. 9.2 Programming Output Voltage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Thermal Shutdown
      2. 10.1.2 Power Loss Estimation
      3. 10.1.3 Inductor Selection
      4. 10.1.4 Output Capacitor Selection
      5. 10.1.5 Input Capacitor Selection
      6. 10.1.6 Catch Diode Selection
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

PWP Package
16-Pin HTSSOP With PowerPAD IC Package
Top View
LM26400Y 20200202.png
NHQ Package
16-Pin WSON
Top View
LM26400Y 20200203.png

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
AVIN 4 PWR Input supply for generating the internal bias used by the entire IC and for generating the internal bootstrap bias. Needs to be locally bypassed.
BST1 16 O Supply rail for the gate drive of Channel 1's NMOS switch. A bootstrap capacitor should be placed between the BST1 and SW1 pins.
BST2 9 O Supply rail for the gate drive of Channel 2's NMOS switch. A bootstrap capacitor should be placed between the BST2 and SW2 pins.
EN1 3 I Enable control input for Channel 1. Logic high enables operation. Do not allow this pin to float or be greater than VIN + 0.3 V.
EN2 6 I Enable control input for Channel 2. Logic high enables operation. Do not allow this pin to float or be greater than VIN + 0.3 V.
FB1 1 I Feedback pin of Channel 1. Connect FB1 to an external voltage divider to set the output voltage of Channel 1.
FB2 8 I Feedback pin of Channel 2. Connect FB2 to an external voltage divider to set the output voltage of Channel 2.
GND 5 PWR Signal and Power ground pin. Kelvin connect the lower resistor of the feedback voltage divider to this pin for good load regulation.
PVIN 11, 12, 13,14 PWR Input voltage of the power supply. Directly connected to the drain of the internal NMOS switch. Tie these pins together and connect to a local bypass capacitor.
SS1 2 I Soft start pin of Channel 1. Connect a capacitor between this pin and ground to program the start up speed.
SS2 7 I Soft start pin of Channel 2. Connect a capacitor between this pin and ground to program the start up speed.
SW2 10 O Switch node of Channel 2. Connects to the inductor, catch diode, and bootstrap capacitor.
SW1 15 O Switch node of Channel 1. Connects to the inductor, catch diode, and bootstrap capacitor.
Die Attach Pad DAP — Must be connected to system ground for low thermal impedance and low grounding inductance.
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