SNVS135E September 1999 – December 2014 LM2660
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LM2660 CMOS charge-pump voltage converter is a versatile unregulated switched capacitor inverter or doubler. Operating from a wide 1.5 V to 5.5 V supply voltage, the LM2660 uses two low-cost capacitors to provide 100 mA of output current without the cost, size and EMI related to inductor-based converters. With an operating current of only 120 µA and operating efficiency greater than 90% at most loads, the LM2660 provides ideal performance for battery-powered systems. LM2660 devices can be operated directly in parallel to lower output impedance, thus providing more current at a given voltage.
The main application of LM2660 is to generate a negative supply voltage. The voltage inverter circuit uses only two external capacitors as shown in the Figure 14. The range of the input supply voltage is 1.5 V to 5.5 V. For a supply voltage less than 3.5V, the LV pin must be connected to ground to bypass the internal regulator circuitry. This gives the best performance in low voltage applications. If the supply voltage is greater than 3.5 V, LV may be connected to ground or left open. The choice of leaving LV open simplifies the direct substitution of the LM2660 for the LMC7660 Switched Capacitor Voltage Converter.
The output characteristics of this circuit can be approximated by an ideal voltage source in series with a resistor. The voltage source equals −(V+). The output resistance Rout is a function of the ON resistance of the internal MOS switches, the oscillator frequency, and the capacitance and ESR of C1 and C2. A good approximation is:
where
High value, low ESR capacitors will reduce the output resistance. Instead of increasing the capacitance, the oscillator frequency can be increased to reduce the 2/(fosc × C1) term. Once this term is trivial compared with RSW and ESRs, further increasing in oscillator frequency and capacitance will become ineffective.
The peak-to-peak output voltage ripple is determined by the oscillator frequency, and the capacitance and ESR of the output capacitor C2:
Again, using a low ESR capacitor will result in lower ripple.
The output resistance and ripple voltage are dependent on the capacitance and ESR values of the external capacitors. The output voltage drop is the load current times the output resistance, and the power efficiency is
where
Since the switching current charging and discharging C1 is approximately twice as the output current, the effect of the ESR of the pumping capacitor C1 is multiplied by four in the output resistance. The output capacitor C2 is charging and discharging at a current approximately equal to the output current, therefore, its ESR only counts once in the output resistance. However, the ESR of C2 directly affects the output voltage ripple. Therefore, low ESR capacitors (Table 2) are recommended for both capacitors to maximize efficiency, reduce the output voltage drop and voltage ripple. For convenience, C1 and C2 are usually chosen to be the same.
The output resistance varies with the oscillator frequency and the capacitors. In Figure 15, the output resistance vs. oscillator frequency curves are drawn for three different tantalum capacitors. At very low frequency range, capacitance plays the most important role in determining the output resistance. Once the frequency is increased to some point (such as 20 kHz for the 150 μF capacitors), the output resistance is dominated by the ON resistance of the internal switches and the ESRs of the external capacitors. A low value, smaller size capacitor usually has a higher ESR compared with a bigger size capacitor of the same type. For lower ESR, use ceramic capacitors.
MANUFACTURER | CAPACITOR TYPE |
---|---|
Nichicon Corp. | PL, PF series, through-hole aluminum electrolytic |
AVX Corp. | TPS series, surface-mount tantalum |
Sprague | 593D, 594D, 595D series, surface-mount tantalum |
Sanyo | OS-CON series, through-hole aluminum electrolytic |
Any number of LM2660s can be paralleled to reduce the output resistance. Each device must have its own pumping capacitor C1, while only one output capacitor Cout is needed as shown in Figure 16. The composite output resistance is:
Cascading the LM2660s is an easy way to produce a greater negative voltage (as shown in Figure 17). If n is the integer representing the number of devices cascaded, the unloaded output voltage Vout is (−nVin). The effective output resistance is equal to the weighted sum of each individual device:
A three-stage cascade circuit shown in Figure 18 generates −3 Vin, from Vin.
Cascading is also possible when devices are operating in doubling mode. In Figure 19, two devices are cascaded to generate 3 Vin.
An example of using the circuit in Figure 18 or Figure 19 is generating +15 V or −15 V from a +5 V input.
Note that, the number of n is practically limited since the increasing of n significantly reduces the efficiency and increases the output resistance and output voltage ripple.
It is possible to regulate the output of the LM2660 by use of a low dropout regulator (such as LP2951). The whole converter is depicted in Figure 20. This converter can give a regulated output from −1.5 V to −5.5 V by choosing the proper resistor ratio:
where
The error flag on pin 5 of the LP2951 goes low when the regulated output at pin 4 drops by about 5%. The LP2951 can be shutdown by taking pin 3 high.
Also, as shown in Figure 21 by operating LM2660 in voltage doubling mode and adding a linear regulator (such as LP2981) at the output, we can get +5 V output from an input as low as +3 V.
The LM2660 can operate as a positive voltage doubler (as shown in the Figure 24). The doubling function is achieved by reversing some of the connections to the device. The input voltage is applied to the GND pin with an allowable voltage from 2.5 V to 5.5 V. The V+ pin is used as the output. The LV pin and OUT pin must be connected to ground. The OSC pin can not be driven by an external clock in this operation mode. The unloaded output voltage is twice of the input voltage and is not reduced by the diode D1's forward drop.
The Schottky diode D1 is only needed for start-up. The internal oscillator circuit uses the V+ pin and the LV pin (connected to ground in the voltage doubler circuit) as its power rails. Voltage across V+ and LV must be larger than 1.5 V to insure the operation of the oscillator. During start-up, D1 is used to charge up the voltage at V+ pin to start the oscillator; also, it protects the device from turning-on its own parasitic diode and potentially latching-up. Therefore, the Schottky diode D1 should have enough current carrying capability to charge the output capacitor at start-up, as well as a low forward voltage to prevent the internal parasitic diode from turning-on. A Schottky diode like 1N5817 can be used for most applications. If the input voltage ramp is less than 10V/ms, a smaller Schottky diode like MBR0520LT1 can be used to reduce the circuit size.
See Application Curves in the Voltage Inverter section.