10.1.2 Gate Drive Layout

The LM27402 high- and low-side gate drivers incorporate short propagation delays, adaptive deadtime control and low-impedance output stages capable of delivering large peak currents with very fast rise and fall times to facilitate rapid turn-on and turn-off transitions of the power MOSFETs. Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled.

Minimization of stray/parasitic loop inductance is key to optimizing gate drive switching performance, whether it be series gate inductance that resonates with MOSFET gate capacitance or common source inductance (common to gate and power loops) that provides a negative feedback component opposing the gate drive command, thereby increasing MOSFET switching times. The following loops are important:

• Loop 3: high-side MOSFET, Q₁. During the high-side MOSFET turn on, high current flows from the boot capacitor through the gate driver and high-side MOSFET, and back to negative terminal of the boot capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from gate of the high-side MOSFET through the gate driver and SW, and back to source of the high-side MOSFET through the SW trace. Refer to loop 3 of Figure 48.
• Loop 4: low-side MOSFET, Q₂. During the low-side MOSFET turn on, high current flows from VDD decoupling capacitor through the gate driver and low-side MOSFET, and back to negative terminal of the capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from gate of the low-side MOSFET through the gate driver and GND, and back to source of the low-side MOSFET through ground. Refer to loop 4 of Figure 48.

The following circuit layout guidelines are strongly recommended when designing with high-speed MOSFET gate drive circuits.

1. Connections from gate driver outputs, HG and LG, to the respective gate of the high-side or low-side MOSFET should be as short as possible to reduce series parasitic inductance. Use 0.65 mm (25 mils) or wider traces. Use via(s), if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HG and SW gate traces as a differential pair from the LM27403 to the high-side MOSFET, taking advantage of flux cancellation.
2. Minimize the current loop path from the VDD and CBOOT pins through their respective capacitors as these provide the high instantaneous current to charge the MOSFET gate capacitances. Specifically, locate the bootstrap capacitor, C_BOOT, close to the LM27402's CBOOT and SW pins to minimize the area of loop 3 associated with the high-side driver. Similarly, locate the VDD capacitor, C_VDD, close to the LM27402's VDD and GND pins to minimize the area of loop 4 associated with the low-side driver.
3. Placing a 2-Ω to 10-Ω BOOT resistor in series with the BOOT capacitor slows down the high-side MOSFET turn-on transition, serving to reduce the voltage ringing and peak amplitude at the SW node at the expense of increased MOSFET turn-on power loss.