6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
|
MIN |
MAX |
UNIT |
Supply voltage (V+ to GND, or V+ to VOUT) |
|
5.8 |
V |
SD |
(GND − 0.3) |
(V+ + 0.3) |
V |
VOUT continuous output current |
|
40 |
mA |
Output short-circuit duration to GND(3) |
|
1 |
sec |
Continuous power dissipation (TA = 25°C)(4)
|
|
600 |
mW |
TJMax(4) |
|
150 |
°C |
Storage temperature, Tstg |
−65 |
150 |
°C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/ Distributors for availability and specifications.
(3) VOUT may be shorted to GND for one second without damage. For temperatures above 85°C, VOUT must not be shorted to GND or device may be damaged.
(4) The maximum allowable power dissipation is calculated by using PDMax = (TJMax − TA)/RθJA, where TJMax is the maximum junction temperature, TA is the ambient temperature, and RθJA is the junction-to-ambient thermal resistance of the specified package.
6.2 ESD Ratings
|
VALUE |
UNIT |
V(ESD) |
Electrostatic discharge |
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) |
±2000 |
V |
Machine model (CDM), per JEDEC specification JESD22-C101(2) |
±200 |
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.5 Electrical Characteristics
Unless otherwise specified, typical limits are for TJ = 25°C, minimum and maximum limits apply over the full operating temperature range: V+ = 5 V, C1 = C2 = 10 μF.(1)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
V+ |
Supply voltage |
|
1.8 |
|
5.5 |
V |
IQ |
Supply current |
No load |
|
350 |
950 |
µA |
ISD |
Shutdown supply current |
TJ = 25°C |
|
0.1 |
0.5 |
µA |
TA = 85°C |
|
0.2 |
|
VSD |
Shutdown pin input voltage |
|
0.6 |
|
|
V |
|
|
|
2 |
IL |
Output current |
2.5 V ≤ VIN ≤ 5.5 V |
20 |
|
|
mA |
1.8 V ≤ VIN ≤ 2.5 V |
10 |
|
|
ROUT |
Output resistance(2) |
IL = 15 mA |
|
20 |
55 |
Ω |
ƒOSC |
Oscillator frequency |
See(3) |
220 |
400 |
700 |
kHz |
ƒSW |
Switching frequency |
See(3) |
110 |
200 |
350 |
kHz |
PEFF |
Power efficiency |
IL = 20 mA to GND |
|
94% |
|
|
VOEFF |
Voltage conversion efficiency |
No load |
|
99.96% |
|
|
(1) In the test circuit, capacitors C1 and C2 are 10-µF, 0.3-Ω maximum ESR capacitors. Capacitors with higher ESR may increase output resistance, and reduce output voltage and efficiency.
(2) Specified output resistance includes internal switch resistance and capacitor ESR. See the details in
Application and Implementation for positive voltage doubler.
(3) The output switches operate at one half of the oscillator frequency, ƒOSC = 2 × ƒSW.