10.1 Layout Guidelines

Some layout guidelines should be followed to ensure proper regulation of the output voltage with minimum noise. Traces carrying the load current should be wide to reduce the amount of parasitic trace inductance and the feedback loop from V_OUT to ADJ should be kept as short as possible. To improve PSRR, a bypass capacitor can be placed at the ADJ pin and should be located as close as possible to the IC. In cases when V_IN shorts to ground, an external diode should be placed from V_OUT to V_IN to divert the surge current from the output capacitor and protect the IC. Similarly, in cases when a large bypass capacitor is placed at the ADJ pin and V_OUT shorts to ground, an external diode should be placed from ADJ to V_OUT to provide a path for the bypass capacitor to discharge. These diodes should be placed close to the corresponding IC pins to increase their effectiveness.