ZHCSE56O August 2012 – December 2015 LM3262
PRODUCTION DATA.
10 Layout
10.1 Layout Guidelines
PC board layout is critical to successfully designing a DC-DC converter into a product. As much as a 20-dB improvement in RX noise floor can be achieved by carefully following recommended layout practices. A properly planned board layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding circuitry while also addressing manufacturing issues that can have adverse impacts on board quality and final product yield.
Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC converter device, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or degraded performance of the converter.
10.1.1 Energy Efficiency
Minimize resistive losses by using wide traces between the power components and doubling up traces on multiple layers when possible.
10.1.2 EMI
By its very nature, any switching converter generates electrical noise, and the design challenge is to minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the LM3262, switches Ampere level currents within nanoseconds, and the traces interconnecting the associated components can act as radiating antennas. The following guidelines are offered to help to ensure that EMI is maintained within tolerable levels.
To minimize radiated noise:
- Place the LM3262 switcher, input capacitor, output filter inductor, and output filter capacitor close together, making the interconnecting traces as short as possible.
- Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor, through the internal PFET of the LM3262 and the inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground, through the internal synchronous NFET of the LM3262 by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
- Make the current loop area(s) as small as possible.
To minimize ground-plane noise:
- Reduce the amount of switching current that circulates through the ground plane — connect the ground bumps of the LM3262 and its input filter capacitor together using generous component-side copper fill as a pseudo-ground plane. Then connect this copper fill to the system ground-plane (if one is used) with multiple vias. These multiple vias help to minimize ground bounce at the LM3262 by giving it a low-impedance ground connection.
To minimize coupling to the voltage feedback trace of the DC-DC converter:
- Route noise sensitive traces, such as the voltage feedback path, as directly as possible from the switcher FB pad to the VOUT pad of the output capacitor, but keep it away from noisy traces between the power components.
To decouple common power supply lines, series impedances may be used to strategically isolate circuits:
- Take advantage of the inherent inductance of circuit traces to reduce coupling among function blocks, by way of the power supply traces.
- Use star connection for separately routing VBATT to PVIN and VBATT_PA.
- Inserting a single ferrite bead in-line with a power supply trace may offer a favorable tradeoff in terms of board area by allowing the use of fewer bypass capacitors.
10.1.3 Manufacturing Considerations
The LM3262 package employs a 9-pin, 3-mm × 3-mm array of 250 micron solder balls, with a 0.4-mm pad pitch. The following simple design rules go a long way to ensuring a good layout:
- The pad size must be 0.225 ± 0.02 mm, and the solder mask opening must be 0.325 ± 0.02 mm.
- As a thermal relief, connect to each pad with 7-mil wide, 7-mil long traces, incrementally increasing each trace to its optimal width. Symmetry is important to ensure the solder bumps re-flow evenly (refer to AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009)).
10.2 Layout Examples
Figure 29. Simplified LM3262 RF Evaluation Board Schematic
- Bulk Input Capacitor C2 must be placed closer to LM3262 than C1.
- Add a 1-nF (C1) on input of LM3262 for high frequency filtering.
- Bulk Output Capacitor C3 must be placed closer to LM3262 than C4.
- Add a 1-nF (C4) on output of LM3262 for high frequency filtering.
- Connect both GND terminals of C1 and C4 directly to system GND layer of phone board.
- Connect bumps SGND (A2), NC (B2), BPEN (C1) directly to System GND.
- Use 0402 caps for both C2 and C3 due to better high frequency filtering characteristics over 0603 capacitors.
- TI has seen some improvement in high-frequency filtering for small bypass caps (C1 and C4) when they are connected to System GND instead of same ground as PGND. These capacitors should be 01005 case size for minimum footprint and best high frequency characteristics.
Figure 30. LM3262 Recommended Parts Placement (Top View)
10.2.1 Component Placement
- PVIN
- Use a star connection from PVIN to LM3262 and PVIN to PA VBATT connection (VCC1). Do not daisy-chain PVIN connection to LM3262 circuit and then to PA device PVIN connection.
- TOP LAYER
- Place a via in LM3262 SGND(A2), BPEN(C1) pads to drop and connect directly to System GND Layer 4.
- Place two vias at LM3262 SW solder bump to drop VSW trace to Layer 3.
- Connect C2 and C3 capacitor GND pads to PGND bump on LM3262 using a star connection. Place vias in C2 and C3 GND pads that connect directly to System GND Layer 4.
- Add 01005/0201 capacitor footprints (C1, C4) to input/output of LM3262 for improved high frequency filtering. C1 and C4 GND pads connect directly to System GND Layer 4.
- Place three vias at L1 inductor pad to bring up VSW trace from Layer 3 to Top Layer.
- LAYER 2
- Make FB trace at least 10 mils (0.254 mm) wide.
- Isolate FB trace away from noisy nodes and connect directly to C3 output capacitor. Place a via in LM3262 SGND (A2), BPEN (C1) pads to drop and connect directly to System GND Layer 4.
- LAYER 3
- Make VSW trace at least 15 mils (0.381 mm) wide.
- LAYER 4 (System GND)
- Connect C2 and C3 PGND vias to this layer.
- Connect C1 and C4 GND vias to this layer.
- Connect LM3262 SGND (A2), BPEN (C1), and NC (B2) pad vias to this layer.
Figure 31. Board Layer 1 — PVIN and PGND Routing
Figure 32. Board Layer 2 — FB and PVIN Routing
Figure 33. Board Layer 3 — SW, VCON and EN Routing
Figure 34. Board Layer 4 — System GND Plane
10.3 DSBGA Assembly and Use
Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow techniques, as detailed in AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). Refer to the section regarding surface mount technology assembly. For best results in assembly, alignment ordinals on the PC board must be used to facilitate placement of the device. The pad style used with DSBGA package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap from holding the device off the surface of the board and interfering with mounting. See SNVA009 for specific instructions on how to do this.
The 9-pin package used for the LM3262 has 250 micron solder balls and requires 0.225-mm pads for mounting on the circuit board. The trace to each pad must enter the pad with a 90° angle to prevent debris from being caught in deep corners. Initially, as a thermal relief, the trace to each pad must be a width of 7 mil for a section approximately 7 mil long. Each trace must neck up or down to its optimal width. The important criterion is symmetry. This ensures the solder bumps on the LM3262 re-flow evenly, and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A3 and C3. Because VIN and PGND are typically connected to large copper planes, inadequate thermal reliefs can result in late or inadequate re-flow of these bumps.
The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA devices are sensitive to light, in the red and infrared range, shining on exposed die edges of the package.
TI recommends using a 10-nF capacitor between VCON and ground for non-standard ESD events or environments and manufacturing processes to prevent unexpected output voltage drift.