SNVSB95 July 2019 LM3421-Q1 , LM3423-Q1
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Current Regulators
- 8.3.2 Predictive Off-Time (PRO) Control
- 8.3.3 Average LED Current
- 8.3.4 Analog Dimming
- 8.3.5 Current Sense and Current Limit
- 8.3.6 Overcurrent Protection
- 8.3.7 Zero Current Shutdown
- 8.3.8 Control Loop Compensation
- 8.3.9 Start-Up Regulator
- 8.3.10 Overvoltage Lockout (OVLO)
- 8.3.11 Input Undervoltage Lockout (UVLO)
- 8.3.12 PWM Dimming
- 8.3.13 LM3423-Q1 Only: DPOL, FLT, TIMR, and LRDY
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1
Basic Topology Schematics
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Operating Point
- 9.2.1.2.2 Switching Frequency
- 9.2.1.2.3 Average LED Current
- 9.2.1.2.4 Inductor Ripple Current
- 9.2.1.2.5 LED Ripple Current
- 9.2.1.2.6 Peak Current Limit
- 9.2.1.2.7 Loop Compensation
- 9.2.1.2.8 Input Capacitance
- 9.2.1.2.9 N-channel FET
- 9.2.1.2.10 Diode
- 9.2.1.2.11 Output OVLO
- 9.2.1.2.12 Input UVLO
- 9.2.1.2.13 PWM Dimming Method
- 9.2.1.2.14 Analog Dimming Method
- 9.2.2
LM3421 Buck-Boost Application
- 9.2.2.1 Design Requirements
- 9.2.2.2
Detailed Design Procedure
- 9.2.2.2.1 Operating Point
- 9.2.2.2.2 Switching Frequency
- 9.2.2.2.3 Average LED Current
- 9.2.2.2.4 Inductor Ripple Current
- 9.2.2.2.5 Output Capacitance
- 9.2.2.2.6 Peak Current Limit
- 9.2.2.2.7 Loop Compensation
- 9.2.2.2.8 Input Capacitance
- 9.2.2.2.9 N-channel FET
- 9.2.2.2.10 Diode
- 9.2.2.2.11 Input UVLO
- 9.2.2.2.12 Output OVLO
- 9.2.2.3 Application Curve
- 9.2.3 LM3421-Q1 BOOST Application
- 9.2.4 LM3421-Q1 Buck-Boost Application
- 9.2.5 LM3423-Q1 Boost Application
- 9.2.6 LM3421 Buck-Boost Application
- 9.2.7 LM3423 Buck Application
- 9.2.8 LM3423 Buck-Boost Application
- 9.2.9 LM3421 SEPIC Application
- 9.2.1
Basic Topology Schematics
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
9.2.1.2.7 Loop Compensation
Using a simple first order peak current mode control model, neglecting any output capacitor ESR dynamics, the necessary loop compensation can be determined.
First, the uncompensated loop gain (TU) of the regulator can be approximated:
Buck
Boost and Buck-Boost
Where the pole (ωP1) is approximated:
Buck
Boost
Buck-Boost
And the RHP zero (ωZ1) is approximated:
Boost
Buck-Boost
And the uncompensated DC loop gain (TU0) is approximated:
Buck
Boost
Buck-Boost
For all topologies, the primary method of compensation is to place a low frequency dominant pole (ωP2), which ensures that there is ample phase margin at the crossover frequency. This is accomplished by placing a capacitor (CCMP) from the COMP pin to AGND, which is calculated according to the lower value of the pole and the RHP zero of the system (shown as a minimizing function):
If analog dimming is used, CCMP should be approximately 4× larger to maintain stability as the LEDs are dimmed to zero.
A high-frequency compensation pole (ωP3) can be used to attenuate switching noise and provide better gain margin. Assuming RFS = 10 Ω, CFS is calculated according to the higher value of the pole and the RHP zero of the system (shown as a maximizing function):
The total system loop gain (T) can then be written as:
Buck
Boost and Buck-Boost
