SNVSB96 July   2019 LM3424-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Typical Boost Application Circuit
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Current Regulators
      2. 7.3.2  Peak Current Mode Control
      3. 7.3.3  Average LED Current
      4. 7.3.4  Thermal Foldback and Analog Dimming
      5. 7.3.5  Current Sense and Current Limit
      6. 7.3.6  Slope Compensation
      7. 7.3.7  Control Loop Compensation
      8. 7.3.8  Start-Up Regulator and Soft-Start
      9. 7.3.9  Overvoltage Lockout (OVLO)
      10. 7.3.10 Input Undervoltage Lockout (UVLO)
        1. 7.3.10.1 UVLO Only
        2. 7.3.10.2 PWM Dimming and UVLO
      11. 7.3.11 PWM Dimming
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Inductor
      2. 8.1.2 LED Dynamic Resistance
      3. 8.1.3 Output Capacitor
      4. 8.1.4 Input Capacitors
      5. 8.1.5 Main MOSFET and Dimming MOSFET
      6. 8.1.6 Re-Circulating Diode
      7. 8.1.7 Switching Frequency
    2. 8.2 Typical Applications
      1. 8.2.1 Basic Topology Schematics
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Operating Point
          2. 8.2.1.2.2  Switching Frequency
          3. 8.2.1.2.3  Average LED Current
          4. 8.2.1.2.4  Thermal Foldback
          5. 8.2.1.2.5  Inductor Ripple Current
          6. 8.2.1.2.6  LED Ripple Current
          7. 8.2.1.2.7  Peak Current Limit
          8. 8.2.1.2.8  Slope Compensation
          9. 8.2.1.2.9  Loop Compensation
          10. 8.2.1.2.10 Input Capacitance
          11. 8.2.1.2.11 NFET
          12. 8.2.1.2.12 Diode
          13. 8.2.1.2.13 Output OVLO
          14. 8.2.1.2.14 Input UVLO
          15. 8.2.1.2.15 Soft-Start
          16. 8.2.1.2.16 PWM Dimming Method
          17. 8.2.1.2.17 Analog Dimming Method
      2. 8.2.2 Buck-Boost Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Operating Point
          2. 8.2.2.2.2  Switching Frequency
          3. 8.2.2.2.3  Average LED Current
          4. 8.2.2.2.4  Thermal Foldback
          5. 8.2.2.2.5  Inductor Ripple Current
          6. 8.2.2.2.6  Output Capacitance
          7. 8.2.2.2.7  Peak Current Limit
          8. 8.2.2.2.8  Slope Compensation
          9. 8.2.2.2.9  Loop Compensation
          10. 8.2.2.2.10 Input Capacitance
          11. 8.2.2.2.11 NFET
          12. 8.2.2.2.12 Diode
          13. 8.2.2.2.13 Input UVLO
          14. 8.2.2.2.14 Output OVLO
          15. 8.2.2.2.15 Soft-Start
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Boost Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
      4. 8.2.4 Buck-Boost Application
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedures
      5. 8.2.5 Boost Application
        1. 8.2.5.1 Design Requirements
        2. 8.2.5.2 Detailed Design Procedure
      6. 8.2.6 Buck-Boost Application
        1. 8.2.6.1 Design Requirements
        2. 8.2.6.2 Detailed Design Procedure
      7. 8.2.7 Buck Application
        1. 8.2.7.1 Design Requirements
        2. 8.2.7.2 Detailed Design Procedure
      8. 8.2.8 Buck-Boost Application
        1. 8.2.8.1 Design Requirements
        2. 8.2.8.2 Detailed Design Procedure
      9. 8.2.9 SEPIC Application
        1. 8.2.9.1 Design Requirements
        2. 8.2.9.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Input Supply Current Limit
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

VIN = 14 V, TA = TJ = −40°C to 125°C unless otherwise specified. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
START-UP REGULATOR (VCC)
VCC-REG VCC Regulation ICC = 0 mA 6.3 7.35 V
ICC = 0 mA, TJ = 25°C 6.9
ICC-LIM VCC Current Limit VCC = 0 V 20 mA
VCC = 0 V, TJ = 25°C 25
IQ Quiescent Current EN = 3 V, Static 3 mA
EN = 3 V, Static, TJ = 25°C 2
ISD Shutdown Current EN = 0 V, TJ = 25°C 0.1 1 µA
VCC-UVLO VCC UVLO Threshold VCC Increasing 4.5 V
VCC Increasing, TJ = 25°C 4.17
VCC Decreasing 3.7 V
VCC Decreasing, TJ = 25°C 4.08
VCC-HYS VCC UVLO Hysteresis TJ = 25°C 0.1 V
ENABLE (EN)
VEN-ST EN start-up Threshold EN Increasing 2.4 V
EN Increasing, TJ = 25°C 1.75
EN Decreasing 0.8 V
EN Decreasing, TJ = 25°C 1.63
VEN-HYS EN start-up Hysteresis TJ = 25°C 0.1 V
REN EN pulldown resistance 0.245 2.85 MΩ
TJ = 25°C 0.82
OVERVOLTAGE PROTECTION (OVP)
VTH-OVP OVP OVLO Threshold OVP Increasing 1.185 1.285 V
OVP Increasing, TJ = 25°C 1.24
IHYS-OVP OVP Hysteresis Source Current OVP Active (high) 13 27 µA
OVP Active (high), TJ = 25°C 20
ERROR AMPLIFIER
VCSH CSH Reference Voltage With Respect to GND 1.21 1.26 V
With Respect to GND, TJ = 25°C 1.235
Error Amplifier Input Bias Current TJ = 25°C –0.6 0 0.6 µA
COMP Sink / Source Current 17 35 µA
TJ = 25°C 26
Transconductance TJ = 25°C 100 µA/V
Linear Input Range See(1), TJ = 25°C ±125 mV
Transconductance Bandwidth –6-dB Unloaded Response(1),
TJ = 25°C		 1 MHz
OSCILLATOR (RT)
fSW Switching Frequency RT = 36 kΩ 164 250 kHz
RT = 36 kΩ, TJ = 25°C 207
RT = 12 kΩ 525 669 kHz
RT = 12 kΩ, TJ = 25°C 597
VRT-SYNC Sync Threshold TJ = 25°C 3.5 V
PWM COMPARATOR
VCP-BASE COMP to PWM Offset - No Slope Compensation 750 1050 mV
TJ = 25°C 900
SLOPE COMPENSATION (SLOPE)
ΔVCP Slope Compensation Amplitude Additional COMP to PWM Offset - SLOPE sinking 100 µA,
TJ = 25°C		 85 mV
CURRENT LIMIT (IS)
VLIM Current Limit Threshold 215 275 mV
TJ = 25°C 245
VLIM Delay to Output 75 ns
TJ = 25°C 35
tON-MIN Leading Edge Blanking Time 140 340 ns
TJ = 25°C 240
HIGH-SIDE TRANSCONDUCTANCE AMPLIFIER
Input Bias Current TJ = 25°C 10 µA
Transconductance 20 mA/V
Input Offset Current –1.5 1.5 µA
TJ = 25°C 0
Input Offset Voltage –5 5 mV
TJ = 25°C 0
Transconductance Bandwidth ICSH = 100 µA(1), TJ = 25°C 500 kHz
GATE DRIVER (GATE)
RSRC-GATE GATE Sourcing Resistance GATE = High 6 Ω
GATE = High, TJ = 25°C 2
RSNK-GATE GATE Sinking Resistance GATE = Low 4.5 Ω
GATE = Low, TJ = 25°C 1.3
UNDERVOLTAGE LOCKOUT AND DIM INPUT (nDIM)
VTH-nDIM nDIM / UVLO Threshold 1.185 1.240 1.285 V
IHYS-nDIM nDIM Hysteresis Current 13 20 27 µA
DIM DRIVER (DDRV)
RSRC-DDRV DDRV Sourcing Resistance DDRV = High 30 Ω
DDRV = High, TJ = 25°C 13.5
RSNK-DDRV DDRV Sinking Resistance DDRV = Low 10 Ω
DDRV = Low, TJ = 25°C 3.5
nDIM rising to DDRV rising 700 ns
nDIM falling to DDRV falling 360 ns
SOFT-START (SS)
ISS Soft-start current 10 µA
THERMAL CONTROL
VS VS Voltage IVS = 0 A,
IVS = 1 mA		 2.4 2.5 V
IVS = 0 A,
IVS = 1 mA,
TJ = 25°C		 2.45
TREF input bias current VTREF = 1.5 V
VTSENSE = 1.5 V, TJ = 25°C		 0.1 µA
TSENSE Input Bias Current VTREF = 1.5 V
VTSENSE = 1.5 V, TJ = 25°C		 0.1 µA
ITGAIN-MAX TGAIN Maximum Sourcing Current VTGAIN = 2 V 200 µA
VTGAIN = 2 V, TJ = 25°C 600
ITF CSH Current with High-side Amplifier Disabled RTGAIN = 10 kΩ, TJ = 25°C VTREF = 1.5 V
VTSENSE = 0.5 V 		100 µA
VTREF = 1.5 V
VTSENSE = 1.4 V 		10 µA
VTREF = 1.5 V
VTSENSE = 1.5 V		 2 µA
THERMAL SHUTDOWN
TSD Thermal Shutdown Threshold See(1), TJ = 25°C 165 °C
THYS Thermal Shutdown Hysteresis See(1), TJ = 25°C 25 °C
(1) These electrical parameters are ensured by design, and are not verified by test.
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