Table 1. Design Parameters

8.2.2.1 Step by Step Design Procedure

To begin the design process, the following items must be considered:

• Output current rating
• Input voltage range
• Output voltage
• Input voltage ripple
• Output voltage ripple

8.2.2.2 Inductor Selection (L1)

The important parameters for the inductor are the inductance and the current rating. The LM3485 operates over a wide frequency range and can use a wide range of inductance values. A good rule of thumb is to use the equations used for Simple Switcher®. The equation for inductor ripple (Δi) as a function of output current (I_OUT) for I_out < 2.0 Amps is Equation 7:

For I_out > 2.0 Amps, follow Equation 8:

The inductance can be calculated based upon the desired operating frequency using Equation 9 and Equation 10:

Equation 9.

Equation 10.

where

• D is the duty cycle
• V_D is the diode forward voltage
• V_DS is the voltage drop across the PFET

The inductor should be rated using Equation 11 and Equation 12:

Equation 12.

The inductance value and the resulting ripple is one of the key parameters controlling operating frequency. The second is the ESR.

8.2.2.3 Output Voltage Set Point

The output voltage (VOUT) can be programmed by two external resistors. It can be calculated using Equation 13.

Refer to Typical Application. A good starting point is to select R2 to be in the range of 10 kΩ to 20 kΩ.

8.2.2.4 Output Capacitor Selection (C_OUT)

The ESR of the output capacitor times the inductor ripple current is equal to the output ripple of the regulator. However, the V_HYST sets the first order value of this ripple. As ESR is increased with a given inductance, then operating frequency increases as well. If ESR is reduced then the operating frequency reduces.

The use of ceramic capacitors has become a common practice of many power supply designers. However, ceramic capacitors have a very low ESR resulting in a 90° phase shift of the output voltage ripple. This results in low operating frequency and increased output ripple. To fix this problem a low value resistor should be added in series with the ceramic output capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance provides highly accurate control over the output voltage ripple. The other types of capacitors, such as Sanyo POS CAP and OS-CON, Panasonic SP CAP, Nichicon NA series, are also recommended and may be used without additional series resistance.

For all practical purposes, any type of output capacitor may be used with proper circuit verification.

8.2.2.5 Input Capacitor Selection (C_IN)

A bypass capacitor is required between the input source and ground. It must be located near the source pin of the external PFET. The input capacitor prevents large voltage transients at the input and provides the instantaneous current when the PFET turns on.

The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the manufacturer's recommended voltage derating. For high input voltage application, low ESR electrolytic capacitor, the Nichicon UD series or the Panasonic FK series, is available. The RMS current in the input capacitor can be calculated using Equation 14.

Equation 14.

The input capacitor power dissipation can be calculated using Equation 15.

The input capacitor must be able to handle the RMS current and the P_D. Several input capacitors may be connected in parallel to handle large RMS currents. In some cases it may be much cheaper to use multiple electrolytic capacitors than a single low ESR, high performance capacitor such as OS-CON or Tantalum. The capacitance value should be selected such that the ripple voltage created by the charge and discharge of the capacitance is less than 10% of the total ripple across the capacitor.

8.2.2.6 Programming the Current Limit (R_ADJ)

The current limit is determined by connecting a resistor (R_ADJ) between input voltage and the ADJ pin.

Using the minimum value for I_{CL_ADJ} (3.0 µA) ensures that the current limit threshold will be set higher than the peak inductor current.

The R_ADJ value must be selected to ensure that the voltage at the ADJ pin does not fall below 3.5 V. With this in mind,

If a larger R_ADJ value is needed to set the desired current limit, either use a PFET with a lower R_DSON, or use a current sense resistor as shown in Figure 26.

The current limit function can be disabled by connecting the ADJ pin to ground and ISENSE to V_IN.

8.2.2.7 Catch Diode Selection (D1)

The important parameters for the catch diode are the peak current, the peak reverse voltage, and the average power dissipation. The average current through the diode can be calculated using Equation 18.

The off state voltage across the catch diode is approximately equal to the input voltage. The peak reverse voltage rating must be greater than input voltage. In nearly all cases a Schottky diode is recommended. In low output voltage applications a low forward voltage provides improved efficiency. For high temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance.

8.2.2.8 P-Channel MOSFET Selection (Q1)

The important parameters for the PFET are the maximum Drain-Source voltage (V_DS), the on resistance (R_DSON), Current rating, and the input capacitance.

The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The V_DS must be selected to provide some margin beyond the input voltage.

PFET drain current, Id, must be rated higher than the peak inductor current, I_IND-PEAK.

Depending on operating conditions, the PGATE voltage may fall as low as V_IN – 8.3 V. Therefore, a PFET must be selected with a V_GS greater than the maximum PGATE swing voltage.

As input voltage decreases below 9 V, PGATE swing voltage may also decrease. At 5.0-V input the PGATE will swing from V_IN to V_IN – 4.6 V. To ensure that the PFET turns on quickly and completely, a low threshold PFET should be used when the input voltage is less than 7 V.

However, PFET switching losses will increase as the V_GS threshold decreases. Therefore, whenever possible, a high threshold PFET should be selected. Total power loss in the FET can be approximated using Equation 19:

A value from 10 ns to 20 ns is typical for t_on and t_off.

A PFET should be selected with a turn on rise time of less than 100 ns. Slower rise times will degrade efficiency, can cause false current limiting, and in extreme cases may cause abnormal spiking at the PGATE pin.

The R_DSON is used in determining the current limit resistor value, R_ADJ.

Keeping the gate capacitance below 2000 pF is recommended to keep switching losses and transition times low. This will also help keep the PFET drive current low, which will improve efficiency and lower the power dissipation within the controller.

As gate capacitance increases, operating frequency should be reduced and as gate capacitance decreases operating frequency can be increased.