5 Pin Configuration and Functions

Figure 5-1 QFN-28RHF PackageTop View

Table 5-1 Pin Functions

PIN		DESCRIPTION
NO.	NAME	DESCRIPTION
1	MODE	1.38 V < MODE < 2.22 V : CCM, Hiccup Enabled (Set R_MODE resistor to AGND = 93.1 kΩ). 2.6 V < MODE < VCC: CCM, Hiccup Disabled (Set R_MODE resistor to AGND = 200 kΩ or connect to VCC)
2	DITH	A capacitor connected between the DITH pin and AGND is charged and discharged with a current source. As the voltage on the DITH pin ramps up and down the oscillator frequency is modulated by 10% of the nominal frequency set by the RT resistor. Grounding the DITH pin will disable the dithering feature. In the external Sync mode, the DITH pin voltage is ignored.
3	RT/SYNC	Switching frequency programming pin. An external resistor is connected to the RT/SYNC pin and AGND to set the switching frequency. This pin can also be used to synchronize the PWM controller to an external clock.
4	SLOPE	A capacitor connected between the SLOPE pin and AGND provides the slope compensation ramp for stable current mode operation in both buck and boost mode.
5	SS	Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time.
6	COMP	Output of the error amplifier. An external RC network connected between COMP and AGND compensates the regulator feedback loop.
7	AGND	Analog ground of the IC.
8	FB	Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter to the FB pin.
9	VOSNS	V_OUT sense input. Connect to the power stage output rail.
10 11	ISNS(–) ISNS(+)	Input or Output Current Sense Amplifier inputs. An optional current sense resistor connected between ISNS(+) and ISNS(–) can be located either on the input side or on the output side of the converter. If the sensed voltage across the ISNS(+) and ISNS(-) pins reaches 50 mV, a slow Constant Current (CC) control loop becomes active and starts discharging the soft-start capacitor to regulate the drop across ISNS(+) and ISNS(-) to 50 mV. Short ISNS(+) and ISNS(-) together to disable this feature.
12	CSG	The negative or ground input to the PWM current sense amplifier. Connect directly to the low-side (ground) of the current sense resistor.
13	CS	The positive input to the PWM current sense amplifier.
14	PGOOD	Power Good open drain output. PGOOD is pulled low when FB is outside a -9%/+10% regulation window around the 0.8-V V_REF.
15 25	SW2 SW1	The boost and the buck side switching nodes respectively.
16 24	HDRV2 HDRV1	Output of the high-side gate drivers. Connect directly to the gates of the high-side MOSFETs.
17 23	BOOT2 BOOT1	An external capacitor is required between the BOOT1, BOOT2 pins and the SW1, SW2 pins respectively to provide bias to the high-side MOSFET gate drivers.
18 22	LDRV2 LDRV1	Output of the low-side gate drivers. Connect directly to the gates of the low-side MOSFETs.
19	PGND	Power ground of the IC. The high current ground connection to the low-side gate drivers.
20	VCC	Output of the VCC bias regulator. Connect capacitor to ground.
21	BIAS	Optional input to the VCC bias regulator. Powering VCC from an external supply instead of V_IN can reduce power loss at high V_IN. For V_BIAS > 8 V, the VCC regulator draws power from the BIAS pin.
26	EN/UVLO	Enable pin. For EN/UVLO < 0.4 V, the LM34936 is in a low current shutdown mode. For EN/UVLO > 1.22 V, the PWM function is enabled, provided VCC exceeds the VCC UV threshold.
27	VIN	The input supply pin to the IC. Connect V_IN to a supply voltage between 4.2 V and 30 V.
28	VISNS	V_IN sense input. Connect to power stage input rail.
-	PowerPAD™	The PowerPAD should be soldered to the analog ground. If possible, use thermal vias to connect to a PCB ground plane for improved power dissipation.