10.1 Layout Guidelines

Figure 12 shows an example of a PCB layout of LM385x-1.2-MIL. Some key V_ref niose considerations are:

• Connect a low-ESR, 0.1-μF (C_L) ceramic bypass capacitor on the cathode pin node.
• Decouple other active devices in the system per the device specifications.
• Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible and only make perpendicular crossings when absolutely necessary.

10.2 Layout Example

Figure 12. Layout Diagram