7.3.9 Internal Compensation and C_FF

The LM46000 is internally compensated with R_C = 400 kΩ and C_C = 50 pF as shown in Functional Block Diagram. The internal compensation is designed such that the loop response is stable over the entire operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. An external feed-forward cap C_FF is recommended to be placed in parallel with the top resistor divider R_FBT for optimum transient performance.

Figure 43. Feed-Forward Capacitor for Loop Compensation

The feed-forward capacitor C_FF in parallel with R_FBT places an additional zero before the cross over frequency of the control loop to boost phase margin. The zero frequency can be found by

An additional pole is also introduced with C_FF at the frequency of

Select the C_FF so that the bandwidth of the control loop without the C_FF is centered between f_Z-CFF and f_P-CFF. The zero f_Z-CFF adds phase boost at the crossover frequency and improves transient response. The pole f_P-CFF helps maintaining proper gain margin at frequency beyond the crossover.

Designs with different combinations of output capacitors need different C_FF. Different types of capacitors have different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most C_FF. Electrolytic capacitors have much larger ESR and the ESR zero frequency low enough to boost the phase up around the crossover frequency. Designs using mostly electrolytic capacitors at the output may not need any C_FF:

The C_FF creates a time constant with R_FBT that couples in the attenuated output voltage ripple to the FB node. If the C_FF value is too large, it can couple too much ripple to the FB and affect V_OUT regulation. It could also couple too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, calculate C_FF based on output capacitors used in the system. At cold temperatures, the value of C_FF might change based on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of C_FF can be reduced. See Detailed Design Procedure for the calculation of C_FF.