ZHCSCN3B June   2014  – March 2018 LM46000

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化原理图
      2.      辐射发射图 VOUT = 3.3V,VIN = 24V,FS= 500kHz,IOUT = 0.5A
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency, Peak-Current-Mode Controlled Step-Down Regulator
      2. 7.3.2  Light Load Operation
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  Enable (EN)
      5. 7.3.5  VCC, UVLO, and BIAS
      6. 7.3.6  Soft Start and Voltage Tracking (SS/TRK)
      7. 7.3.7  Switching Frequency (RT) and Synchronization (SYNC)
      8. 7.3.8  Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions
      9. 7.3.9  Internal Compensation and CFF
      10. 7.3.10 Bootstrap Voltage (CBOOT)
      11. 7.3.11 Power Good (PGOOD)
      12. 7.3.12 Overcurrent and Short-Circuit Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 CCM Mode
      5. 7.4.5 Light Load Operation
      6. 7.4.6 Self-Bias Mode
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Output Capacitor Selection
        7. 8.2.2.7  Feed-Forward Capacitor
        8. 8.2.2.8  Bootstrap Capacitors
        9. 8.2.2.9  VCC Capacitor
        10. 8.2.2.10 BIAS Capacitors
        11. 8.2.2.11 Soft-Start Capacitors
        12. 8.2.2.12 Undervoltage Lockout Setpoint
        13. 8.2.2.13 PGOOD
      3. 8.2.3 Application Performance Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
      2. 10.1.2 Ground Plane and Thermal Considerations
      3. 10.1.3 Feedback Resistors
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 使用 WEBENCH® 工具创建定制设计
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to minimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In Buck converters, the pulsing current path is from the VIN side of the input capacitors to HS switch, to the LS switch, and then return to the ground of the input capacitors, as shown in Figure 100.

LM46000 Buck-didt.gifFigure 100. Buck Converter High di / dt Path

High-frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction.

The SW pin connecting to the inductor must be as short as possible and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper pours (shapes) for high current condution path to minimize parasitic resistance. Place the output capacitors close to the VOUT end of the inductor and closely grounded to PGND pin and exposed PAD.

Place he bypass capacitors on VCC and BIAS pins as close as possible to the pins respectively and closely grounded to PGND and the exposed PAD.