ZHCSGO2H September 2003 – November 2018 LM5007
PRODUCTION DATA.
The input capacitor should be large enough to limit the input voltage ripple that can be calculated using Equation 14.
The input ripple reaches its maximum at D = 0.5. Targeting a ΔVCIN = 0.5 V at using a duty cycle of D = 0.5 results in CIN = 0.526 µF. A standard value of 1 µF is selected. The input capacitor should be rated for the maximum input voltage under all conditions. A 100-V, X7R type capacitor is selected for this design. The input capacitor should be placed close to the VIN pin and the anode of the diode (D1) as it supplies high-frequency switching current.
Also place a 0.1-µF bypass capacitor (CBYP) very close to VIN and RTN pins of the IC to reduce switching power loop parasitic inductance and mitigate SW node overshoot and ringing.