10.1 Layout Guidelines

The LM5010 regulation, overvoltage, and current limit comparators are very fast, and respond to short duration noise pulses. Therefore, layout considerations are critical for optimum performance. The layout must be as neat and compact as possible, and all the components must be as close as possible to their associated pins. The current loop formed by D1, L1 (L_IND), C2 (C_OUT), and the S_GND and I_SEN pins should be as small as possible. The ground connection from C2 (C_OUT) to C1 (C_IN) should be as short and direct as possible. If it is expected that the internal dissipation of the LM5010 will produce high junction temperatures during normal operation, good use of the PC board’s ground plane can help considerably to dissipate heat. The exposed pad on the IC package bottom can be soldered to a ground plane, and that plane should both extend from beneath the IC, and be connected to exposed ground plane on the board’s other side using as many vias as possible. The exposed pad is internally connected to the IC substrate.

The use of wide PC board traces at the pins, where possible, can help conduct heat away from the IC. The four no connect pins on the HTSSOP package are not electrically connected to any part of the IC, and may be connected to ground plane to help dissipate heat from the package. Judicious positioning of the PC board within the end product, along with the use of any available air flow (forced or natural convection) can help reduce the junction temperature.

10.2 Layout Example

Figure 18. LM5010 Buck Layout Example With the WSON Package