米6体育平台手机版

SNVS376F October 2005 – May 2016 LM5010A , LM5010A-Q1

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PWP|14
- MPDS370A
DPR|10
- MPSS046B

散热焊盘机械数据 (封装 | 引脚)

PWP|14
- PPTD287A

订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
VIN	6	75	V
VIN to RTN	–0.3	76	V
BST to RTN	–0.3	90	V
SW to RTN (steady state)		–1.5	V
BST to VCC		76	V
BST to SW		14	V
VCC to RTN	–0.3	14	V
S_GND to RTN	–0.3	0.3	V
SS to RTN	–0.3	4	V
VIN to SW		76	V
All other inputs to RTN	–0.3	7	V
Lead temperature (soldering, 4 sec)⁽²⁾		260	°C
Junction temperature (LM5010A, Q1,Q0)	–40	150	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) For detailed information on soldering plastic HTSSOP and WSON packages, see Mechanical, Packaging, and Orderable Information.

6.2 ESD Ratings: LM5010A

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings: LM5010A-Q1, LM5010-Q0

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾⁽²⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011⁽³⁾	±750	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_IN	Input voltage		6	75	V
I_O	Output current			1	A
Ext-V_CC	External bias voltage⁽¹⁾		8	13	V
T_J	Operating junction temperature	LM5010A	–40	125	°C
T_J	Operating junction temperature	LM5010A-Q1, LM5010-Q0	–40	150	°C

(1) V_CC provides bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.

6.5 Thermal Information

THERMAL METRIC⁽¹⁾		LM5010A, LM5010A-Q1		UNIT
		DPR (WSON)	PWP (HTSSOP)
		10 PINS	14 PINS
R_θJA	Junction-to-ambient thermal resistance	36	41.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	31.9	26.5	°C/W
R_θJB	Junction-to-board thermal resistance	13.2	22.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	0.7	°C/W
ψ_JB	Junction-to-board characterization parameter	13.5	22.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3	3.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

Typical values correspond to T_J = 25°C, minimum and maximum limits apply over T_J = –40°C to 125°C, V_IN = 48 V, and
R_ON = 200 kΩ (unless otherwise noted).⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_CC REGULATOR
V_CCReg	VCC regulated output		6.6	7	7.4	V
	V_IN - V_CC	I_CC = 0 mA, F_S < 200 kHz, 6 V ≤ V_IN ≤ 8.5 V		100		mV
	V_CC Bypass threshold	V_IN increasing		8.9		V
	V_CC Bypass hysteresis	V_IN decreasing		260		mV
	V_CC Output impedance (0 mA ≤ I_CC ≤ 5 mA)	V_IN = 6 V		55		Ω
		V_IN = 8 V		50
		V_IN = 48 V		0.21
	V_CC Current limit	V_IN = 48 V, V_CC = 0 V		15		mA
UVLO_VCC	V_CC undervoltage lockout threshold	V_CC increasing		5.25		V
	UVLO_VCC hysteresis	V_CC decreasing		180		mV
	UVLO_VCC filter delay	100 mV overdrive		3		µs
	I_IN Operating current	Non-switching, FB = 3 V		675	950	µA
	I_IN Shutdown current	R_ON/SD = 0 V		100	200	µA
SOFT-START PIN
I_SS	Internal current source		8	11.5	15	µA
CURRENT LIMIT
I_LIM	Threshold	Current out of I_SEN	1	1.25	1.5	A
	Resistance from I_SEN to S_GND			130		mΩ
	Response time			150		ns
ON TIMER, R_ON/SD PIN
	Shutdown threshold	Voltage at R_ON/SD rising	0.3	0.7	1.05	V
	Threshold hysteresis			40		mV
REGULATION AND OVER-VOLTAGE COMPARATORS (FB PIN)
V_REF	FB regulation threshold	T_J ≤ 125°C	2.445	2.5	2.55	V
		T_J ≤ 150°C, over full operating junction temperature range	2.435
			2.44
	FB overvoltage threshold			2.9		V
	FB bias current			1		nA
THERMAL SHUTDOWN
T_SD	Thermal shutdown temperature			175		°C
T_SD	Thermal shutdown hysteresis			20		°C

(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

6.7 Switching Characteristics

Typical values correspond to T_J = 25°C, minimum and maximum limits apply over T_J = –40°C to 125°C, and V_IN = 48 V (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
R_DS(ON)	Buck switch	I_SW = 200 mA	T_J ≤ 125°C		0.35	0.8	Ω
R_DS(ON)	Buck switch	I_SW = 200 mA	T_J ≤ 150°C, over full operating junction temperature range			0.85	Ω
UVLO_GD	Gate drive UVLO	V_BST - V_SW increasing		1.7	3	4	V
	UVLO_GD Hysteresis				400		mV
OFF TIMER
t_OFF	Minimum OFF-time				260		ns
ON TIMER
t_ON - 1	ON-time	V_IN = 10 V, R_ON = 200 kΩ		2.1	2.75	3.4	µs
t_ON - 2	ON-time	V_IN = 75 V, R_ON = 200 kΩ		290	390	496	ns

(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations while applying statistical process control.

Figure 1. Start-Up Sequence

6.8 Typical Characteristics

at T_A = 25°C (unless otherwise noted)

Figure 2. V_CC vs V_IN

Figure 4. I_CC vs Externally Applied V_CC

Figure 6. Voltage at R_ON/SD Pin

Figure 3. V_CC vs I_CC

Figure 5. ON-Time vs V_IN and R_ON

Figure 7. I_IN vs V_IN