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SNVS699H February 2011 – January 2015 LM5045

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PWP|28
- MPDS373B
RSG|28
- MPQF190A

散热焊盘机械数据 (封装 | 引脚)

PWP|28
- PPTD290A

订购信息

6 Specifications

6.1 Absolute Maximum Ratings ⁽¹⁾

	MIN	MAX	UNIT
VIN to GND	–0.3	105	V
HS to GND⁽²⁾	–5	105	V
BST1/BST2 to GND	–0.3	116	V
BST1/BST2 to HS1/HS2	–0.3	16	V
HO1/HO2 to HS1/HS2⁽¹⁾	–0.3	BST1/BST2 + 0.3	V
LO1/LO2/SR1/SR2⁽¹⁾	–0.3	V_CC + 0.3	V
V_CC to GND	–0.3	16	V
REF,SSOFF,RT,OVP,UVLO to GND	–0.3	7	V
RAMP	–0.3	7	V
COMP		–0.3	V
COMP Input Current		10	mA
All other inputs to GND⁽¹⁾	–0.3	REF + 0.3	V
Junction Temperature		150	°C
Storage temperature, T_stg	–55	150	°C

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
VIN Voltage	14	100	V
External Voltage Applied to VCC	10	14	V
Junction Temperature	–40	125	°C
SLOPE	–0.3	2	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM5045		UNIT
		PWP	RSG
		28 PINS
R_θJA	Junction-to-ambient thermal resistance	40	40	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	4	4	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Limits in standard typeface are for T_J = 25°C only; MIN and MAX limits apply the junction temperature range of –40°C to 125°C. Unless otherwise specified, the following conditions apply: V_IN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ. No load on HO1, HO2, LO1, LO2, SR1, SR2, COMP = 0 V, UVLO = 2.5 V, OVP = 0 V, SSOFF = 0 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
START-UP REGULATOR (V_CC PIN)
V_CC1	V_CC voltage	I_CC= 10 mA (SSSR < 1 V)	9.3	9.6	9.9	V
V_CC2	V_CC voltage	I_CC= 10 mA (SSSR > 1 V)	7.5	7.8	8.1	V
I_CC(Lim)	V_CC current limit	V_CC= 6 V	60	80		mA
I_CC(ext)	V_CC supply current	Supply current into VCC from an externally applied source. V_CC = 10 V		4.6		mA
	V_CC load regulation	I_CC from 0 to 50 mA		35		mV
V_CC(UV)	V_CC undervoltage threshold	Positive going VCC	V_CC1–0.2	V_CC1–0.1		V
V_CC(UV)	V_CC undervoltage threshold	Negative going VCC	5.9	6.3	6.7	V
I_IN	V_IN operating current			4		mA
	V_IN shutdown current	V_IN = 20 V, V_UVLO = 0 V		300	520	µA
	V_IN shutdown current	V_IN = 100 V, V_UVLO = 0 V		350	550	µA
	V_IN start-up regulator leakage	V_CC=10 V		160		µA
VOLTAGE REFERENCE REGULATOR (REF PIN)
V_REF	REF voltage	I_REF = 0 mA	4.85	5	5.15	V
	REF voltage regulation	I_REF = 0 to 10 mA		25	50	mV
I_REF(Lim)	REF current limit	V_REF = 4.5 V	15	20		mA
V_REFUV	V_REF undervoltage threshold	Positive going V_REF	4.3	4.5	4.7	V
V_REFUV	Hysteresis			0.25		V
UNDERVOLTAGE LOCK OUT AND SHUTDOWN (UVLO PIN)
V_UVLO	Under-voltage threshold		1.18	1.25	1.32	V
I_UVLO	Hysteresis current	UVLO pin sinking current when V_UVLO < 1.25 V	16	20	24	µA
	Undervoltage standby enable threshold	UVLO voltage rising	0.32	0.4	0.48	V
	Hysteresis			0.05		V
V_OVP	OVP shutdown threshold	OVP rising	1.18	1.25	1.32	V
	OVP hysteresis current	OVP sources current when OVP > 1.25 V	16	20	24	µA
SOFT-START (SS PIN)
I_SS	SS charge current	V_SS = 0 V	16	20	24	µA
	SS threshold for SSSR charge current enable	I_COMP < 800 µA	1.93	2	2.2	V
	SS output low voltage	Sinking 100 µA		40		mV
	SS threshold to disable switching			200		mV
I_SSSR	SSSR charge current	V_SS > 2 V, I_COMP < 800 µA	16	20	24	µA
I_SSSR-DIS1	SSSR discharge current 1	V_UVLO < 1.25 V	54	65	75	µA
I_SSSR-DIS2	SSSR discharge current 2	V_RES > 1 V	109	125	147	µA
	SSSR output low voltage	Sinking 100 µA		50		mV
	SSSR threshold to enable SR1/SR2			1.2		V
CURRENT SENSE INPUT (CS PIN)
V_CS	Current limit threshold		0.71	0.75	0.785	V
	CS delay to output			65		ns
	CS leading edge blanking			50		ns
R_CS	CS sink impedance (clocked)	Internal FET sink impedance		18	45	Ω
SOFT-STOP DISABLE (SS OFF PIN)
V_IH(min)	SSOFF Input-threshold			2.8		V
	SSOFF pulldown resistance			200		kΩ
CURRENT LIMIT RESTART (RES Pin)
R_RES	RES pulldown resistance	Termination of hiccup timer		37		Ω
V_RES	RES hiccup threshold			1		V
	RES upper counter threshold			4		V
	RES lower counter threshold			2		V
I_RES-SRC1	Charge current source 1	V_RES< 1 V, V_CS> 750 mV		30		µA
I_RES-SRC2	Charge current source 2	1 V < V_RES < 4 V		10		µA
I_RES-DIS2	Discharge current source 1	V_CS < 750 mV		5		µA
I_RES-DIS2	Discharge current source 2	2 V < V_RES < 4 V		5		µA
	Ratio of time in hiccup mode to time in current limit	V_RES > 1 V, Hiccup counter		147
VOLTAGE FEED-FORWARD (RAMP PIN)
	RAMP sink impedance (Clocked)			5.5	20	Ω
OSCILLATOR (RT PIN)
F_SW1	Frequency (LO1, half oscillator frequency)	R_T = 25 kΩ	185	200	215	kHz
F_SW2	Frequency (LO1, half oscillator frequency)	R_T = 10 kΩ	420	480	540	kHz
	DC level			2		V
	RT sync threshold		2.8	3	3.3	V
SYNCHRONOUS RECTIFIER TIMING CONTROL (RD1 and RD2 PINS)
T1	SR trailing edge delay SR turnoff to HO&LO both on	R_D1 = 20 kΩ	45	65	90	ns
		R_D1 = 100 kΩ	232	300	388	ns
T2	SR leading edge HO or LO turnoff to SR turnon	R_D2 = 20 kΩ	43	65	90	ns
		R_D2 = 100 kΩ	227	300	384	ns
COMP PIN
V_PWM-OS	COMP current to RAMP offset	V_RAMP = 0 V	680	800	940	µA
V_SS-OS	SS to RAMP offset	V_RAMP = 0 V	0.78	1.0	1.22	V
	COMP current to RAMP gain	ΔRAMP/ΔI_COMP		2400		Ω
	SS to RAMP gain	ΔSS/ΔRAMP		0.5
	COMP current for SSSR charge current enable	V_SS > 2 V	690	800	915	µA
	COMP to output delay			120		ns
	Minimum duty cycle	I_COMP = 1 mA			0%
SLOPE COMPENSATION (SLOPE PIN)
I_SLOPE	Slope compensation current ramp	Peak of RAMP current		100		µA
BOOST (BST PIN)
V_{Bst uv}	BST under-voltage threshold	V_BST – V_HS rising	3.8	4.7	5.6	V
	Hysteresis			0.5		V
HO1, HO2, LO1, LO2 GATE DRIVERS
V_OL	Low-state output voltage	I_HO/LO = 100 mA		0.16	0.32	V
V_OH	High-state output voltage	I_HO/LO = 100 mA V_OHL = V_CC – V_LO V_OHH = V_BST – V_HO		0.27	0.495	V
	Rise Time	C-load = 1000 pF		16		ns
	Fall Time	C-load = 1000 pF		11		ns
I_OHL	Peak Source Current	V_HO/LO = 0 V		1.5		A
I_OLL	Peak Sink Current	V_HO/LO = V_CC		2		A
SR1, SR2 GATE DRIVERS
V_OL	Low-state output voltage	I_SR1/SR2 = 10 mA		0.05	0.1	V
V_OH	High-state output voltage	I_SR1/SR2 = 10 mA, V_OH = V_REF – V_SR		0.17	0.28	V
	Rise Time	C-load = 1000 pF		60		ns
	Fall Time	C-load = 1000 pF		20		ns
I_OHL	Peak Source Current	V_SR = 0 V		0.1		A
I_OLL	Peak Sink Current	V_SR = V_REF		0.4		A
THERMAL SHUTDOWN
TSD	Thermal Shutdown Temp			160		°C
	Thermal Shutdown Hysteresis			25		°C

(1) These pins are output pins and as such should not be connected to an external voltage source. The voltage range listed is the limits the internal circuitry is designed to reliably tolerate in the application circuit.

(2) The negative HS voltage must never be more negative than VCC–16 V. For example, if VCC = 12 V, the negative transients at HS must not exceed –4 V.