ZHCSKM9F May 2011 – December 2019 LM5050-1 , LM5050-1-Q1
PRODUCTION DATA.
The typical PCB layout for LM5050-1/-Q1 is shown in Figure 34. TI recommends connecting the IN, Gate and OUT pins close to the source and drain pins of the MOSFET. Keep the traces of the MOSFET drain wide and short to minimize resistive losses. Place surge suppressors (D1 and D4) components as shown in the example layout of LM5050-1 in Layout Example.