8.2.1.2.3 Fault Detection Delay Time

To allow the gate of the MOSFET adequate time to change, and to allow the MOSFET to conduct currents beyond the protection threshold for a brief period of time, a fault delay timer function is provided. This feature is important when drive loads which require a surge of current in excess of the normal ON current upon start up, or at any point in time, such as lamps and motors. A single low leakage capacitor (C_TIMER) connected from the TIMER (pin 7), to ground sets the delay time interval for both the V_GS status detection at start-up and for the subsequent V_DS Over-Current fault detection.

When the LM5060 is enabled under normal operating conditions the timer capacitor will begin charging at a 6 μA (typical) rate while simultaneously charging the gate of the external MOSFET at a 24 μA (typical) rate. The gate-to-source voltage (V_GS) of the external MOSFET is expected to reach the 5-V (typical) threshold before the timer capacitor has charged to the V_TMRH threshold (2 V typical) in order to avoid being shutdown.

While V_GS is less than the typical 5-V threshold (V_GATE-TH), the V_DS start-up fault delay time is calculated from:

Equation 3.

where

• I_TMRL is typically 6 μA and V_TMRH is typically 2 V

If the C_TIMER value is 68 nF (0.068μF) the V_GS start-up fault delay time would typically be:

When the LM5060 has successfully completed the start-up sequence by reaching a V_GS of 5 V within the fault delay time set by the timer capacitor (C_TIMER), the capacitor is quickly discharged to 300 mV (typical) and the charge current is increased to 11 μA (typical) while the gate of the external MOSFET is continued to be charge at a 24 μA (typical) rate. The external MOSFET may not be fully enhanced at this point in time and some additional time may be needed to allow the gate-to-source voltage (V_GS) to charge to a higher value. The drain-to-source voltage (V_DS) of the external MOSFET must fall below the V_DSTH threshold set by R_S and I_SENSE before the timer capacitor has charged to the V_TMRH threshold (2 V typical) to avoid a fault.

When V_GS is greater than the typical 5-V threshold (V_GATE-TH), the V_DS transition fault delay time is calculated from:

Equation 5.

where

• I_TMRH is typically 11 μA
• V_TMRH is typically 2 V
• V_TMRL is typically 300 mV

If the C_TIMER value is 68 nF(0.068 μF) the V_DS transition fault delay time would typically be:

Should a subsequent load current surge trip the V_DS Fault Comparator, the timer capacitor discharge transistor turns OFF and the 11 μA (typical) current source begins linearly charging the timer capacitor. If the surge current, with the detected excessive V_DS voltage, lasts long enough for the timer capacitor to charge to the timing comparator threshold (V_TMRH) of typically 2 V, the LM5060 will immediately discharge the MOSFET gate and latch the MOSFET off. The V_DS fault delay time during an Over-Current event is calculated from:

Equation 7.

where

• I_TMRH is typically 11 μA
• V_TMRH is typically 2 V

If the C_TIMER value is 68 nF(0.068 μF) the V_DS Over-Current fault delay time would typically be:

Since a single capacitor is used to set the delay time for multiple fault conditions, it is likely that some compromise will need to be made between a desired delay time and a practical delay time.