ZHCSCT1A April   2014  – August 2014 LM5066I

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4  简化电路原理图
  5. 5 修订历史记录
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Handling Ratings
    2. 8.2 Recommended Operating Conditions
    3. 8.3 Thermal Information
    4. 8.4 Electrical Characteristics
    5. 8.5 SMBus Communications Timing Requirements and Definitions
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Current Limit
      2. 9.3.2 Circuit Breaker
      3. 9.3.3 Power Limit
      4. 9.3.4 UVLO
      5. 9.3.5 OVLO
      6. 9.3.6 Power Good Pin
      7. 9.3.7 VDD Sub-Regulator
      8. 9.3.8 Remote Temperature Sensing
      9. 9.3.9 Damaged MOSFET Detection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Up Sequence
      2. 9.4.2 Gate Control
      3. 9.4.3 Fault Timer and Restart
      4. 9.4.4 Shutdown Control
      5. 9.4.5 Enabling/Disabling and Resetting
    5. 9.5 Programming
      1. 9.5.1 PMBus Command Support
      2. 9.5.2 Standard PMBus Commands
        1. 9.5.2.1  OPERATION (01h)
        2. 9.5.2.2  CLEAR_FAULTS (03h)
        3. 9.5.2.3  CAPABILITY (19h)
        4. 9.5.2.4  VOUT_UV_WARN_LIMIT (43h)
        5. 9.5.2.5  OT_FAULT_LIMIT (4Fh)
        6. 9.5.2.6  OT_WARN_LIMIT (51h)
        7. 9.5.2.7  VIN_OV_WARN_LIMIT (57h)
        8. 9.5.2.8  VIN_UV_WARN_LIMIT (58h)
        9. 9.5.2.9  STATUS_BYTE (78h)
        10. 9.5.2.10 STATUS_WORD (79h)
        11. 9.5.2.11 STATUS_VOUT (7Ah)
        12. 9.5.2.12 STATUS_INPUT (7Ch)
        13. 9.5.2.13 STATUS_TEMPERATURE (7dh)
        14. 9.5.2.14 STATUS_CML (7Eh)
        15. 9.5.2.15 STATUS_OTHER (7Fh)
        16. 9.5.2.16 STATUS_MFR_SPECIFIC (80h)
        17. 9.5.2.17 READ_EIN (86h)
        18. 9.5.2.18 READ_VIN (88h)
        19. 9.5.2.19 READ_IIN (89h)
        20. 9.5.2.20 READ_VOUT (8Bh)
        21. 9.5.2.21 READ_TEMPERATURE_1 (8Dh)
        22. 9.5.2.22 READ_PIN (97h)
        23. 9.5.2.23 MFR_ID (99h)
        24. 9.5.2.24 MFR_MODEL (9Ah)
        25. 9.5.2.25 MFR_REVISION (9Bh)
      3. 9.5.3 Manufacturer Specific PMBus Commands
        1. 9.5.3.1  MFR_SPECIFIC_00: READ_VAUX (D0h)
        2. 9.5.3.2  MFR_SPECIFIC_01: MFR_READ_IIN (D1h)
        3. 9.5.3.3  MFR_SPECIFIC_02: MFR_READ_PIN (D2h)
        4. 9.5.3.4  MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h)
        5. 9.5.3.5  MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h)
        6. 9.5.3.6  MFR_SPECIFIC_05: READ_PIN_PEAK (D5h)
        7. 9.5.3.7  MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h)
        8. 9.5.3.8  MFR_SPECIFIC_07: GATE_MASK (D7h)
        9. 9.5.3.9  MFR_SPECIFIC_08: ALERT_MASK (D8h)
        10. 9.5.3.10 MFR_SPECIFIC_09: DEVICE_SETUP (D9h)
        11. 9.5.3.11 MFR_SPECIFIC_10: BLOCK_READ (DAh)
        12. 9.5.3.12 MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh)
        13. 9.5.3.13 MFR_SPECIFIC_12: READ_AVG_VIN (DCh)
        14. 9.5.3.14 MFR_SPECIFIC_13: READ_AVG_VOUT (DDh)
        15. 9.5.3.15 MFR_SPECIFIC_14: READ_AVG_IIN (DEh)
        16. 9.5.3.16 MFR_SPECIFIC_14: READ_AVG_PIN (DFh)
        17. 9.5.3.17 MFR_SPECIFIC_15: READ_AVG_PIN
        18. 9.5.3.18 MFR_SPECIFIC_16: BLACK_BOX_READ (E0h)
        19. 9.5.3.19 MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h)
        20. 9.5.3.20 MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h)
      4. 9.5.4 Reading and Writing Telemetry Data and Warning Thresholds
      5. 9.5.5 Determining Telemetry Coefficients Empirically With Linear Fit
      6. 9.5.6 Writing Telemetry Data
      7. 9.5.7 PMBus Address Lines (ADR0, ADR1, ADR2)
      8. 9.5.8 SMBA Response
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 48-V, 10-A PMBus Hotswap Design
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design-In Procedure
          1. 10.2.1.2.1 Select RSNS and CL Setting
          2. 10.2.1.2.2 Selecting the Hotswap FETs
          3. 10.2.1.2.3 Select Power Limit
          4. 10.2.1.2.4 Set Fault Timer
          5. 10.2.1.2.5 Check MOSFET SOA
          6. 10.2.1.2.6 Set UVLO and OVLO Thresholds
            1. 10.2.1.2.6.1 Option A
            2. 10.2.1.2.6.2 Option B
            3. 10.2.1.2.6.3 Option C
            4. 10.2.1.2.6.4 Option D
          7. 10.2.1.2.7 Power Good Pin
          8. 10.2.1.2.8 Input and Output Protection
          9. 10.2.1.2.9 Final Schematic and Component Values
        3. 10.2.1.3 Application Curves
      2. 10.2.2 48-V, 20-A PMBus Hotswap Design
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1  Selecting the Sense Resistor and CL Setting
          2. 10.2.2.2.2  Selecting the Hotswap FETs
          3. 10.2.2.2.3  Select Power Limit
          4. 10.2.2.2.4  Set Fault Timer
          5. 10.2.2.2.5  Check MOSFET SOA
          6. 10.2.2.2.6  Switching to dv/dt-Based Start-Up
          7. 10.2.2.2.7  Choosing the VOUT Slew Rate
          8. 10.2.2.2.8  Select Power Limit and Fault Timer
          9. 10.2.2.2.9  Chose Input and Output Protection and Set Undervoltage, Overvoltage, and Power Good Thresholds
          10. 10.2.2.2.10 Final Schematic and Component Values
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 商标
    2. 13.2 静电放电警告
    3. 13.3 术语表
  14. 14机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Power Supply Recommendations

In general, the LM5066I behavior is more reliable if it is supplied from a very regulated power supply. However, high-frequency transients on a backplane are not uncommon due to adjacent card insertions or faults. If this is expected in the end system, TI recommends to place a 1-µF ceramic capacitor to ground close to the source of the hotswap MOSFET. This reduces the common mode seen by VIN_K and SENSE. Additional filtering may be necessary to avoid nuisance trips.

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