The LM5067 determines the power dissipation in the external MOSFET (Q1) by monitoring the drain current (the current in R_S), and the V_DS of Q1 (OUT to SENSE pins). The resistor at the PWR pin (R_PWR) sets the maximum power dissipation for Q1, and is calculated from the following equation:

where

• P_FET(LIM) is the desired power limit threshold for Q1
• R_S is the current sense resistor described in the Current Limit section

For example, if R_S is 10 mΩ, and the desired power limit threshold is 60W, R_PWR calculates to 85.2 kΩ. If the Q1 power dissipation reaches the power limit threshold, the Q1 gate is modulated to control the load current, keeping Q1 power from exceeding the threshold. For proper operation of the power limiting feature, R_PWR must be ≤150 kΩ. While the power limiting circuit is active, the fault timer is active as described in the Fault Timer and Restart section. Typically, power limit is reached during startup, or when the V_DS of Q1 increases due to a severe overload or short circuit.

The programmed maximum power dissipation should have a reasonable margin relative to the maximum power defined by the SOA chart if the LM5067-2 is used since the FET will be repeatedly stressed during fault restart cycles. The FET manufacturer should be consulted for guidelines. The PWR pin can be left open if the application does not require use of the power limit function.