ZHCSLQ5D October   2007  – August 2020 LM5067

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Up Sequence
      2. 8.3.2 Gate Control
      3. 8.3.3 Current Limit
      4. 8.3.4 Circuit Breaker
      5. 8.3.5 Power Limit
      6. 8.3.6 Fault Timer and Restart
      7. 8.3.7 Undervoltage Lock-Out (UVLO)
      8. 8.3.8 Overvoltage Lock-Out (OVLO)
      9. 8.3.9 Power Good Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown / Enable Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  RIN, CIN
        2. 9.2.2.2  Current Limit, RS
        3. 9.2.2.3  Power Limit Threshold
        4. 9.2.2.4  Turn-On Time
          1. 9.2.2.4.1 Turn-on With Current Limit Only
          2. 9.2.2.4.2 Turn-on With Power Limit and Current Limit
        5. 9.2.2.5  MOSFET Selection
        6. 9.2.2.6  Timer Capacitor, CT
          1. 9.2.2.6.1 Insertion Delay
          2. 9.2.2.6.2 Fault Timeout Period
          3. 9.2.2.6.3 Restart Timing
        7. 9.2.2.7  UVLO, OVLO
          1. 9.2.2.7.1 Option A:
          2. 9.2.2.7.2 Option B:
          3. 9.2.2.7.3 Option C:
          4. 9.2.2.7.4 Option D:
        8. 9.2.2.8  Thermal Considerations
        9. 9.2.2.9  System Considerations
          1. 9.2.2.9.1 System Considerations During Surge Events
        10. 9.2.2.10 Power Good Pin
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Operating Voltage
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 静电放电警告
    3. 12.3 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Pin Functions

Name Pin I/O Description
VSSOP-10 SOIC-14
VCC 1 1 I Positive supply input: Connect to system ground through a resistor. Connect a bypass capacitor to VEE. The voltage from VCC to VEE is nominally 13 V set by an internal zener diode.
UVLO/EN 2 3 I Under-voltage lockout: An external resistor divider from the system input voltage sets the under-voltage turn-on threshold. The enable threshold at the pin is 2.5 V above VEE. An internal 22 µA current source provides hysteresis. This pin can be used for remote enable and disable.
OVLO 3 4 I Overvoltage lockout: An external resistor divider from the system input voltage sets the overvoltage turn-off threshold. The disable threshold at the pin is 2.5 V above VEE. An internal 22 µA current source provides hysteresis.
PWR 4 5 I Power limit set: An external resistor at this pin, in conjunction with the current sense resistor (RS), sets the maximum power dissipation in the external series pass MOSFET.
VEE 5 6 I Negative supply input: Connect to the system negative supply voltage (typically -48V).
TIMER 6 8 I/O Timing capacitor: An external capacitor at this pin sets the insertion time delay and the fault timeout period. The capacitor also sets the restart timing of the LM5067-2.
SENSE 7 9 I Current sense input: The voltage across the current sense resistor (RS) is measured from VEE to this pin. If the voltage across RS reaches 50 mV the load current is limited and the fault timer activates.
GATE 8 10 O Gate drive output: Connect to the external N-channel MOSFET’s gate.
OUT 9 12 I Output feedback: Connect to the external MOSFET’s drain. Internally used to determine the MOSFET VDS voltage for power limiting, and to control the PGD output pin.
PGD 10 14 0 Power Good indicator: An open drain output capable of sustaining 80 V when off. When the external MOSFET VDS decreases below 1.23 V the PGD pin switches high. When the external MOSFET VDS increases above ≊2.5 V the PGD pin switches low.
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