The Power Good output indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET. An external pull-up resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin must be more positive than VEE, and can be up to 80V above VEE with transient capability to 100 V. PGD is switched high at the end of the turn-on sequence when the voltage from OUT to SENSE (the external MOSFET’s V_DS) decreases below 1.23 V. PGD switches low if the MOSFET’s V_DS increases past 2.5 V, if the system input voltage goes below the UVLO threshold or above the OVLO threshold, or if a fault is detected. The PGD output is high when the operating voltage (VCC-VEE) is less than 2 V.