ZHCSLQ5D October   2007  – August 2020 LM5067

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Up Sequence
      2. 8.3.2 Gate Control
      3. 8.3.3 Current Limit
      4. 8.3.4 Circuit Breaker
      5. 8.3.5 Power Limit
      6. 8.3.6 Fault Timer and Restart
      7. 8.3.7 Undervoltage Lock-Out (UVLO)
      8. 8.3.8 Overvoltage Lock-Out (OVLO)
      9. 8.3.9 Power Good Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown / Enable Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  RIN, CIN
        2. 9.2.2.2  Current Limit, RS
        3. 9.2.2.3  Power Limit Threshold
        4. 9.2.2.4  Turn-On Time
          1. 9.2.2.4.1 Turn-on With Current Limit Only
          2. 9.2.2.4.2 Turn-on With Power Limit and Current Limit
        5. 9.2.2.5  MOSFET Selection
        6. 9.2.2.6  Timer Capacitor, CT
          1. 9.2.2.6.1 Insertion Delay
          2. 9.2.2.6.2 Fault Timeout Period
          3. 9.2.2.6.3 Restart Timing
        7. 9.2.2.7  UVLO, OVLO
          1. 9.2.2.7.1 Option A:
          2. 9.2.2.7.2 Option B:
          3. 9.2.2.7.3 Option C:
          4. 9.2.2.7.4 Option D:
        8. 9.2.2.8  Thermal Considerations
        9. 9.2.2.9  System Considerations
          1. 9.2.2.9.1 System Considerations During Surge Events
        10. 9.2.2.10 Power Good Pin
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Operating Voltage
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 静电放电警告
    3. 12.3 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11.1 Layout Guidelines

The following guidelines should be followed when designing the PC board for the LM5067:

  • Place the LM5067 close to the board’s input connector to minimize trace inductance from the connector to the FET.
  • Place RIN and CIN close to the VCC and VEE pins to keep transients below the Absolute Maximum rating of the LM5067. Transients of several volts can easily occur when the load current is shut off.
  • The sense resistor (RS) should be close to the LM5067, and connected to it using the Kelvin techniques shown in Figure 9-2.
  • The high current path from the board’s input to the load, and the return path (via Q1), should be parallel and close to each other wherever possible to minimize loop inductance.
  • The VEE connection for the various components around the LM5067 should be connected directly to each other, and to the LM5067’s VEE pin, and then connected to the system VEE at one point. Do not connect the various components to each other through the high current VEE track.
  • Provide adequate heat sinking for the series pass device (Q1) to help reduce thermal stresses during turn-on and turn-off.
  • The board’s edge connector can be designed to shut off the LM5067 as the board is removed, before the supply voltage is disconnected from the LM5067. In Figure 11-1 the voltage at the UVLO/EN pin goes to VEE before VSYS is removed from the LM5067 due to the shorter edge connector pin. When the board is inserted into the edge connector, the system voltage is applied to the LM5067’s VEE and VCC pins before voltage is applied to the UVLO/EN pin.
  • If power dissipation within the LM5067 is high, an exposed copper pad should be provided beneath the package, and that pad should be connected to exposed copper on the board’s other side with as many vias as possible. See Thermal Considerations.
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