ZHCSLQ5D October   2007  – August 2020 LM5067

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Up Sequence
      2. 8.3.2 Gate Control
      3. 8.3.3 Current Limit
      4. 8.3.4 Circuit Breaker
      5. 8.3.5 Power Limit
      6. 8.3.6 Fault Timer and Restart
      7. 8.3.7 Undervoltage Lock-Out (UVLO)
      8. 8.3.8 Overvoltage Lock-Out (OVLO)
      9. 8.3.9 Power Good Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown / Enable Control
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  RIN, CIN
        2. 9.2.2.2  Current Limit, RS
        3. 9.2.2.3  Power Limit Threshold
        4. 9.2.2.4  Turn-On Time
          1. 9.2.2.4.1 Turn-on With Current Limit Only
          2. 9.2.2.4.2 Turn-on With Power Limit and Current Limit
        5. 9.2.2.5  MOSFET Selection
        6. 9.2.2.6  Timer Capacitor, CT
          1. 9.2.2.6.1 Insertion Delay
          2. 9.2.2.6.2 Fault Timeout Period
          3. 9.2.2.6.3 Restart Timing
        7. 9.2.2.7  UVLO, OVLO
          1. 9.2.2.7.1 Option A:
          2. 9.2.2.7.2 Option B:
          3. 9.2.2.7.3 Option C:
          4. 9.2.2.7.4 Option D:
        8. 9.2.2.8  Thermal Considerations
        9. 9.2.2.9  System Considerations
          1. 9.2.2.9.1 System Considerations During Surge Events
        10. 9.2.2.10 Power Good Pin
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Operating Voltage
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 静电放电警告
    3. 12.3 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息
System Considerations During Surge Events

The control MOSFET, Q1, has a body-diode, illustrated in Figure 9-10, where current can freely flow in the reverse direction. The most common cause of a reverse current is a discharge event at the input of the hot-swap circuit when the output capacitance discharges to the input. Normally, reverse current flow presents no issue for hotswap devices during events such as shutdown and minor input power perturbations. However, extreme situations such as high energy lighting surge line disturbances can expose the hot-swap circuit to pulses of ultra fast - high amplitude reverse currents. It is common to observe current amplitudes on the order of 1000 A in these situations. Figure 9-10 illustrates what an extreme input discharge event may look like and how it affects the circuit.

GUID-72DD0520-A861-4E55-BB8F-B6EF55992839-low.gifFigure 9-10 Differential Voltage Across Sense Resistor

Figure 9-10 shows how the induced reverse current spike causes a differential voltage across the sense resistor, VRS, and the Q1 body-diode, VBD. The transient reverse current, IREVERSE, is approximately equal to IREVERSE = COUT x dVIN/dt because the output capacitor is discharged through the input. Faster discharge rates (dVIN/dt) will induce larger IREVERSE currents. If IREVERSE is extremely high, it can cause a large negative voltage at the SENSE and OUT pins with respect to the VEE pin of the LM5067. If the negative absolute maximum voltage rating is greatly exceeded, harmful currents can flow into the affected pins. Series pin resistors can be implemented to limit the pin current caused by the negative voltage excursion. Schottky diodes may also be implemented to completely clamp the voltage at these pins, Figure 9-11 illustrates this.

GUID-865D4DFB-ADC6-4EC1-A692-512C89FC829C-low.gifFigure 9-11 Schottky Diodes Used to Clamp Pin Voltage

A typical value of Rpin can be 22 Ω to effectively limit the pin current during extreme negative voltage spikes. If schottky diodes are used, they only need to be applied to SENSE_K, SENSE, and OUT. Each schottky diode return pin should be coupled closely with the VEE plane to provide the most effective clamping. The schottky diode at OUT should be able to withstand at least 100 V. VEE_K needs a series resistor even though it’s not subjected to negative voltage spikes in order to balance the differential current sense voltage signal. Protecting the SENSE_K, SENSE, and OUT pins from negative voltage spikes will facilitate a robust hot-swap circuit and smooth operation during extreme reverse current surge events.