ZHCSLQ5D October 2007 – August 2020 LM5067
PRODUCTION DATA
If the current limit threshold is less than the current defined by the power limit threshold at maximum VDS the circuit operates only at the current limit threshold during turn-on. Referring to Figure 9-5a, as the drain current reaches ILIM, the gate-to-source voltage is controlled at VGSL to maintain the current at ILIM. As the output voltage reaches its final value (VDS ≊ 0 V) the drain current reduces to the value defined by the load, and the gate is charged to approximately 13 V (VGATE). The time for the OUT pin voltage to transition from zero volts to VSYS is equal to:
where
For example, if VSYS = –48 V, CL = 1000 µF, and ILIM = 1 A, tON calculates to 48 ms. The maximum instantaneous power dissipated in the MOSFET is 48W. This calculation assumes the time from t1 to t2 in Figure 9-5a is small compared to tON, and the load does not draw any current until after the output voltage has reached its final value, and PGD switches high (Figure 9-3).
If the load draws current during the turn-on sequence (Figure 9-4), the turn-on time is longer than the above calculation, and is approximately equal to:
where
The Fault Timeout Period must be set longer than tON to prevent a fault shutdown before the turn-on sequence is complete.