During initial power up, the Power Good pin (PGD) is high until the operating voltage (VCC – VEE) increases above ≊2V. PGD then switches low, remaining low as the system voltage and the operating voltage increase. After Q1 is switched on, when the voltage at the OUT pin is within 1.23 V of the SENSE pin (Q1 V_DS <1.23 V), PGD switches high indicating the output voltage is at, or nearly at, its final value. Any of the following situations will cause PGD to switch low within ≊10 µs:

• The V_DS of Q1 increases above 2.5 V.
• The system input voltage decreases below the UVLO level.
• The system input voltage increase above the OVLO level.
• The TIMER pin increases to 4V due to a fault condition.

A pull-up resistor is required at PGD as shown in Figure 9-12. The pull-up voltage (V_PGD) can be as high as 80 V above VEE, with transient capability to 100 V, and can be higher or lower than the system ground.

Figure 9-12 Power Good Output

If a delay is required at PGD, suggested circuits are shown in the following figure. In Figure 9-13, capacitor C_PG adds delay to the rising edge, but not to the falling edge. In Figure 9-14, the rising edge is delayed by R_PG1 + R_PG2 and C_PG, while the falling edge is delayed a lesser amount by R_PG2 and C_PG. Adding a diode across R_PG2. Figure 9-15 allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.

Figure 9-13 Adding Delay to the Power Good Output Pin - Delay Rising Edge Only

Figure 9-15 Adding Delay to the Power Good Output Pin - Short Delay at Rising Edge and Long Delay at Falling Edge, or Equal Delays

Figure 9-14 Adding Delay to the Power Good Output Pin - Long Delay at Rising Edge, Short Delay at Falling Edge