ZHCSLQ5D October   2007  – August 2020 LM5067

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Up Sequence
      2. 8.3.2 Gate Control
      3. 8.3.3 Current Limit
      4. 8.3.4 Circuit Breaker
      5. 8.3.5 Power Limit
      6. 8.3.6 Fault Timer and Restart
      7. 8.3.7 Undervoltage Lock-Out (UVLO)
      8. 8.3.8 Overvoltage Lock-Out (OVLO)
      9. 8.3.9 Power Good Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown / Enable Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  RIN, CIN
        2. 9.2.2.2  Current Limit, RS
        3. 9.2.2.3  Power Limit Threshold
        4. 9.2.2.4  Turn-On Time
          1. 9.2.2.4.1 Turn-on With Current Limit Only
          2. 9.2.2.4.2 Turn-on With Power Limit and Current Limit
        5. 9.2.2.5  MOSFET Selection
        6. 9.2.2.6  Timer Capacitor, CT
          1. 9.2.2.6.1 Insertion Delay
          2. 9.2.2.6.2 Fault Timeout Period
          3. 9.2.2.6.3 Restart Timing
        7. 9.2.2.7  UVLO, OVLO
          1. 9.2.2.7.1 Option A:
          2. 9.2.2.7.2 Option B:
          3. 9.2.2.7.3 Option C:
          4. 9.2.2.7.4 Option D:
        8. 9.2.2.8  Thermal Considerations
        9. 9.2.2.9  System Considerations
          1. 9.2.2.9.1 System Considerations During Surge Events
        10. 9.2.2.10 Power Good Pin
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Operating Voltage
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 静电放电警告
    3. 12.3 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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9.2.1 Design Requirements

The recommended design-in procedure for the LM5067 is as follows:

  • Determine the minimum and maximum system voltages (VEE). Select the input resistor (RIN) to provide at least 2 mA into the VCC pin at the minimum system voltage. The resistor’s power rating must be suitable for its power dissipation at maximum system voltage ((VSYS – 13V)2/RIN).
  • Determine the current limit threshold (ILIM). This threshold must be higher than the normal maximum load current, allowing for tolerances in the current sense resistor value and the LM5067 Current Limit threshold voltage. Use equation 1 to determine the value for RS.
  • Determine the maximum allowable power dissipation for the series pass FET (Q1), using the device’s SOA information. Use equation 2 to determine the value for RPWR.
  • Determine the value for the timing capacitor at the TIMER pin (CT) using Equation 3. The fault timeout period (tFAULT) must be longer than the circuit’s turn-on-time. The turn-on time can be estimated using the equations in the Turn-on Time section of this data sheet, but should be verified experimentally. Allow for tolerances in the values of the external capacitors, sense resistor, and the LM5067 Electrical Characteristics for the TIMER pin, current limit and power limt. Review the resulting insertion time, and the restart timing if the LM5067-2 is used.
  • Choose option A, B, C, or D from the UVLO, OVLO section of the Application Information for setting the UVLO and OVLO thresholds and hysteresis. Use the procedure in the appropriate option to determine the resistor values at the UVLO and OVLO pins.
  • Choose the appropriate voltage, and pull-up resistor, for the Power Good output.
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