SNVS565I November   2008  – August 2015 LM5085 , LM5085-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM5085
    3. 6.3 ESD Ratings: LM5085-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Regulation Control Circuit
      2. 7.3.2  On-Time Timer
      3. 7.3.3  Shutdown
      4. 7.3.4  Current Limiting
      5. 7.3.5  Current Limit Off-Time
      6. 7.3.6  VCC Regulator
      7. 7.3.7  PGATE Driver Output
      8. 7.3.8  P-Channel MOSFET Selection
      9. 7.3.9  Soft-Start
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode with VIN <4.5 V
      2. 7.4.2 RT Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Components
        2. 8.2.2.2 Alternate Output Ripple Configurations
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • NGQ|8
  • DGK|8
  • DGN|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

8-Pins
HVSSOP Package
Top View
LM5085 LM5085-Q1 30057702.gif
8-Pins
WSON Package
Top View
LM5085 LM5085-Q1 30057704.gif
8-Pins
VSSOP Package
Top View
LM5085 LM5085-Q1 30057703.gif

Pin Functions

PIN I/O DESCRIPTION APPLICATION INFORMATION
NAME NO.
ADJ 1 I Current Limit Adjust The current limit threshold is set by an external resistor from VIN to ADJ in conjunction with the external sense resistor or the PFET’s RDS(ON).
RT 2 I On-Time Control and Shutdown An external resistor from VIN to RT sets the buck switch on-time and switching frequency. Grounding this pin shuts down the controller.
FB 3 I Voltage Feedback From the Regulated Output Input to the regulation and over-voltage comparators. The regulation level is 1.25V.
GND 4 - Circuit Ground Ground reference for all internal circuitry
ISEN 5 I Current Sense Input for Current limit Detection. Connect to the PFET drain when using RDS(ON) current sense. Connect to the PFET source and the sense resistor when using a current sense resistor.
PGATE 6 O Gate Driver Output Connect to the gate of the external PFET.
VCC 7 O Output of the gate driver bias regulator Output of the negative voltage regulator (relative to VIN) that biases the PFET gate driver. A low ESR capacitor is required from VIN to VCC, located as close as possible to the pins.
VIN 8 I Input Supply Voltage The operating input range is from 4.5V to 75V. A low ESR bypass capacitor must be located as close as possible to the VIN and GND pins.
EP - Exposed Pad Exposed pad on the underside of the package (HVSSOP and WSON only). This pad is to be soldered to the PC board ground plane to aid in heat dissipation.
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