SNVS268B May 2004 – December 2014 LM5102
PRODUCTION DATA.
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5102 is one of the latest generation of high voltage gate drivers which are designed to drive both the high-side and low-side N-Channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit. The floating high side driver is capable of operating with supply voltages up to 100 V. This allows for N-Channel MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies.
In the LM5102 the outputs are independently controlled. The rising edge of each output can be independently delayed with a programming resistor.
Table 1. LM5102 Highlights
| FEATURE | BENEFIT |
|---|---|
| Independently programmable high and low side delay | Allows optimisation of gate drive timings to account for device differences between high-side and low-side positions |
| Low power consumption | Improves light load efficiency figures |
| Internal bootstrap diode | Reduces parts count and PCB real estate |
8.2 Typical Application
8.2.1 Design Requirements
| PARAMETERS | VALUES |
|---|---|
| Gate Drive IC | LM5102 |
| Mosfet | CSD18531Q5A |
| VDD | 10 V |
| Qgmax | 43 nC |
| Fsw | 100 kHz |
| DMax | 95% |
| IHBO | 10 µA |
| VDH | 1.1 V |
| VHBR | 7.1 V |
| VHBH | 0.4 V |
8.2.2 Detailed Design Procedure
where
- VDD = Supply voltage of the gate drive IC
- VDH = Bootstrap diode forward voltage drop
- Vgsmin = Minimum gate source threshold voltage
The quiescent current of the bootstrap circuit is 10 µA which is negligible compared to the Qgs of the mosfet.
In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where the power stage may skip pulse due to load transients. In this circumstance the boot capacitor must maintain the HB Pin voltage above the UVLO Voltage for the HB circuit.
As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT.
The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be twice that of the maximum VDD to allow for loss of capacitance once the devices have a dc bias voltage across them and to ensure long term reliability of the devices.
The resistor values, RT1 and RT2, for setting turn on delay can be found in Figure 18.
8.2.3 Application Curves
Figure 17. Application Timing Waveforms
Figure 18. Turn On Delay vs Temperature (RT = 10 k)