ZHCS571I August   2010  – April  2018 LM5119

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用电路
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-Up Regulator
      2. 7.3.2  UVLO
      3. 7.3.3  Enable 2
      4. 7.3.4  Oscillator and Sync Capability
      5. 7.3.5  Error Amplifiers and PWM Comparators
      6. 7.3.6  Ramp Generator
      7. 7.3.7  Current Limit
      8. 7.3.8  Hiccup Mode Current Limiting
      9. 7.3.9  Soft Start
      10. 7.3.10 HO and LO Output Drivers
      11. 7.3.11 Maximum Duty Cycle
      12. 7.3.12 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Diode Emulation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Miscellaneous Functions
      2. 8.1.2 Interleaved Two-Phase Operation
      3. 8.1.3 Interleaved 4-Phase Operation
    2. 8.2 Typical Applications
      1. 8.2.1 Dual-output Design Example
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Timing Resistor
          2. 8.2.1.2.2  Output Inductor
          3. 8.2.1.2.3  Current Sense Resistor
          4. 8.2.1.2.4  Ramp Resistor and Ramp Capacitor
          5. 8.2.1.2.5  Output Capacitors
          6. 8.2.1.2.6  Input Capacitors
          7. 8.2.1.2.7  VCC Capacitor
          8. 8.2.1.2.8  Bootstrap Capacitor
          9. 8.2.1.2.9  Soft-Start Capacitor
          10. 8.2.1.2.10 Restart Capacitor
          11. 8.2.1.2.11 Output Voltage Divider
          12. 8.2.1.2.12 UVLO Divider
            1. 8.2.1.2.12.1 MOSFET Selection
          13. 8.2.1.2.13 MOSFET Snubber
          14. 8.2.1.2.14 Error Amplifier Compensation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Two-Phase Design Example
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Switching Jitter Root Causes and Solutions
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range. VIN = 36 V, VCC = 8 V, VVCCDIS = 0 V, VEN2 = 5 V, RT = 25 kΩ, and no load on LO or HO (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VIN SUPPLY
IBIAS VIN operating current SS1 = SS2 = 0 V 6 7.3 mA
VCCDIS = 2V, SS1 = SS2 = 0 V 400 550 µA
IVCC VCC1 operating current VCCDIS = 2 V, SS1 = SS2 = 0 V 3.9 4.5 mA
VCC2 operating current VCCDIS = 2 V, SS1 = SS2 = 0 V 1.4 2 mA
ISHUTDOWN VIN shutdown current UVLO = 0 V, SS1 = SS2 = 0 V 18 50 µA
VCC REGULATOR(3)
VCC(REG) VCC regulation 6.77 7.6 8.34 V
VIN = 6 V, no external load 5.9 5.95
Sourcing current limit VCC = 0 V 25 40 mA
VCCDIS switch threshold VCCDIS rising 1.19 1.25 1.29 V
VCCDIS switch hysteresis 0.07 V
VCCDIS input current VCCDIS = 0 V –20 nA
Undervoltage threshold Positive going VCC 4.7 4.9 5.2 V
Undervoltage hysteresis 0.2 V
EN2 INPUT
VIL EN2 input low threshold 2 1.5 V
VIH EN2 input high threshold 2.9 2.5 V
EN2 input pullup resistor 50 kΩ
UVLO
Threshold UVLO rising 1.2 1.25 1.29 V
Hysterisis current UVLO = 1.4 V 15 20 25 µA
Shutdown threshold 0.4 V
Shutdown hysteresis voltage 0.1 V
SOFT START
Current source SS = 0 V 7 10 13 µA
Pulldown RDSON 10 Ω
ERROR AMPLIFIER
VREF FB reference voltage Measured at FB pin, FB = COMP 0.788 0.8 0.812 V
FB input bias current FB = 0.8 V 1 nA
FB disable threshold Interleaved threshold 2.5 V
COMP VOH Isource = 3 mA 2.8 V
COMP VOL Isink = 3 mA 0.31 V
AOL DC gain 80 dB
fBW Unity gain bandwidth 3 MHz
PWM COMPARATORS
tHO(OFF) Forced HO OFF-time 220 320 430 ns
tON(min) Minimum HO ON-time CRAMP = 50 pF 100 ns
OSCILLATOR
fSW1 Frequency 1 RT = 25 kΩ 180 200 220 kHz
fSW2 Frequency 2 RT = 10 kΩ 430 480 530 kHz
RT output voltage 1.25 V
RT sync positive threshold 2.5 3.2 4 V
Sync pulse minimum width 100 ns
CURRENT LIMIT
VCS(TH) Cycle-by-cycle sense voltage
threshold (CS – CSG)		 RAMP = 0 106 120 134 mV
CS bias current CS = 0 V –70 –95 µA
Hiccup mode fault timer 256 Cycles
RES
IRES Current source 9.7 µA
VRES Threshold CRES charging 1.2 1.25 1.3 V
DIODE EMULATION
VIL DEMB input low threshold 2 1.65 V
VIH DEMB input high threshold 2.9 2.6 V
DEMB input pulldown resistance 50 kΩ
SW zero cross threshold –5 mV
LO GATE DRIVER
VOLL LO low-state output voltage ILO = 100 mA 0.1 0.18 V
VOHL LO high-state output voltage ILO = –100 mA, VOHL = VCC – VLO 0.17 0.26 V
LO rise time C-load = 1000 pF 6 ns
LO fall time C-load = 1000 pF 5 ns
IOHL Peak LO source current VLO = 0 V 2.5 A
IOLL Peak LO sink current VLO = VCC 3.3 A
HO GATE DRIVER
VOLH HO low-state output voltage IHO = 100 mA 0.11 0.19 V
VOHH HO high-state output voltage IHO = –100 mA, VOHH = VHB – VHO 0.18 0.27 V
HO rise time C-load = 1000 pF 6 ns
HO fall time C-load = 1000 pF 5 ns
IOHH Peak HO Source current VHO = 0 V, SW = 0, HB = 8 V 2.2 A
IOLH Peak HO sink current VHO = VHB = 8 V 3.3 A
HB to SW undervoltage 3 V
HB DC bias current HB – SW = 8 V 70 100 µA
THERMAL
TSD Thermal shutdown Rising 165 °C
Thermal shutdown hysteresis 25 °C
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Texas Instrument's Average Outgoing Quality Level (AOQL).
(2) Typical specifications represent the most likely parametric normal at 25°C operation.
(3) Per VCC Regulator.
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