8.1.2 Interleaved Two-Phase Operation

Interleaved operation can offer many advantages in single-output, high-current applications. The output power path is split between two identical channels reducing the current in each channel by one-half. Ripple current reduction in the output capacitors is reduced significantly because each channel operates 180 degrees out of phase from the other. Ripple reduction is greatest at 50% duty cycle and decreases as the duty cycle varies away from 50%.

Refer to Figure 12 to estimate the ripple current reduction. Also, the effective ripple in the input and output capacitors occurs at twice the frequency of a single-channel design due to the combining of the two channels. All of these factors are advantageous in managing the higher currents and their effects in a high power design.

Figure 12. Cancellation Factor vs Duty Cycle for Output Capacitor

To begin an interleaved design, use the previous equations in this datasheet to first calculate the required value of components using one-half the current in the output power path. The attenuation factor in Figure 12 is the ratio of the output capacitor ripple to the inductor ripple versus duty cycle. The inductor ripple used in this calculation is the ripple in either inductor in a two phase design, not the ripple calculated for a single-phase design of the same output power. It can be observed that operation around 50% duty cycle results in almost complete ripple attenuation in the output capacitor. Figure 12 can be used to calculate the amount of ripple attenuation in the output capacitors.

Figure 13. Normalized Input Capacitor RMS Ripple Current vs Duty Cycle

Figure 13 illustrates the ripple current reduction in the input capacitors due to interleaving. As with the output capacitors, there is near perfect ripple reduction near 50% duty cycle. This plot can be used to calculate the ripple in the input capacitors at any duty cycle. In designs with large duty cycle swings, use the worst-case ripple reduction for the design.

To configure the LM5119 for interleaved operation, connect COMP1 and COMP2 pins together at the IC. Connecting the FB2 pin to VCC2 pin disables the channel2 error amplifier with a high output impedance at COMP2. Connect the compensation network between FB1 and the common COMP pins. Connect the two power stages together at the output capacitors. Finally use the plots in Figure 12 and Figure 13 along with the duty cycle range to determine the amount of output and input capacitor ripple reduction. Frequently more capacitance than necessary is used in a design just to meet ESR requirements. Reducing the capacitance based solely on ripple reduction graphs alone may violate this requirement.