ZHCS571I August 2010 – April 2018 LM5119
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 High Voltage Start-Up Regulator
- 7.3.2 UVLO
- 7.3.3 Enable 2
- 7.3.4 Oscillator and Sync Capability
- 7.3.5 Error Amplifiers and PWM Comparators
- 7.3.6 Ramp Generator
- 7.3.7 Current Limit
- 7.3.8 Hiccup Mode Current Limiting
- 7.3.9 Soft Start
- 7.3.10 HO and LO Output Drivers
- 7.3.11 Maximum Duty Cycle
- 7.3.12 Thermal Protection
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Dual-output Design Example
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Timing Resistor
- 8.2.1.2.2 Output Inductor
- 8.2.1.2.3 Current Sense Resistor
- 8.2.1.2.4 Ramp Resistor and Ramp Capacitor
- 8.2.1.2.5 Output Capacitors
- 8.2.1.2.6 Input Capacitors
- 8.2.1.2.7 VCC Capacitor
- 8.2.1.2.8 Bootstrap Capacitor
- 8.2.1.2.9 Soft-Start Capacitor
- 8.2.1.2.10 Restart Capacitor
- 8.2.1.2.11 Output Voltage Divider
- 8.2.1.2.12 UVLO Divider
- 8.2.1.2.13 MOSFET Snubber
- 8.2.1.2.14 Error Amplifier Compensation
- 8.2.1.3 Application Curves
- 8.2.2 Two-Phase Design Example
- 8.2.1
Dual-output Design Example
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
- 12机械、封装和可订购信息
8.2.1.2.12 UVLO Divider
The UVLO threshold is internally set to 1.25 V at the UVLO pin. The LM5119 is enabled when the system input voltage VIN causes the UVLO pin to exceed the threshold voltage of 1.25 V. When the UVLO pin voltage is below the threshold, the internal 20-μA current source is disabled. When the UVLO pin voltage exceeds the
1.25-V threshold, the 20-μA current source is enabled causing the UVLO pin voltage to increase, providing hysteresis. The values of RUV1 and RUV2 can be determined from Equation 34 and the example (Equation 35).
VHYS is the desired UVLO hysteresis at VIN, and VIN in the second equation is the desired UVLO release (turnon) voltage. For example, if it is desired for the LM5119 to be enabled when VIN reaches 13.5 V, and the desired hysteresis is 1.2 V, then RUV2 must be set to 60 kΩ and RUV1 must be set to 6.12 kΩ. For this application, RUV2 was selected to be 60.4 kΩ, RUV1was selected to be 6.19 kΩ. The LM5119 can be remotely shutdown by taking the UVLO pin below 0.4 V with an external open-collector or open-drain device. The outputs and the VCC regulator are disabled in shutdown mode. Capacitor CFT provides filtering for the divider. A value of 100 pF was chosen for CFT. The voltage at the UVLO pin must never exceed 15 V when using the external set-point divider. It may be necessary to clamp the UVLO pin at high input voltages.
Figure 17. UVLO Configuration