10.1.1 Switching Jitter Root Causes and Solutions

1. Noise coupling of the high frequency switching between two channels through the input power rail
   1. Keep the high current path as short as possible
   2. Choose a FET with minimum lead inductance
   3. Place local bypass capacitors (C_IN1, C_IN2) as close as possible to the high-side FETs to isolate one channel from the high frequency noise of the other channel
   4. Slow down the SW switching speed by increasing gate resistors R29 and R30
   5. Minimize the effective ESR or ESL of the input capacitor by paralleling input capacitors
2. High frequency AC noise on FB, CS, CSG and COMP
   1. Use the star ground PCB layout technique and minimize the length of the high current path
   2. Keep the signal traces away from the SW, HO, HB traces and the inductor
   3. Add an R-C filter between the CS and CSG pins
   4. Place CS filter capacitor (C30, C31) next to the LM5119 and on the same PCB layer as the LM5119
3. Ground offset at the switching frequency
   1. Use the star ground PCB layout technique and minimize the length between the grounds of C_IN1and C_IN2