When SS is greater than 1.5 V, the device enters deep sleep mode after four cycles in OVP status. During deep sleep mode, the device stops the internal oscillator to reduce the operating current, disables UVLO comparator, disables the error amplifier, and parks the COMP pin at 0.25 V.

In FPWM or DE mode, the device re-enters active mode if V_OUT falls down below V_OVTH. In skip mode, the device re-enters active mode if VOUT falls down below V_OVTH, then immediately enters sleep mode after 16 consecutive cycles of pulse skipping.