The switching frequency of the device can be synchronized to an external clock by directly applying an external pulse signal to the SYNC pin. The internal clock is synchronized at the rising edge of the external synchronization pulse using an internal PLL. Connect the SYNC pin to ground if not used.

The external synchronization pulse must be greater than V_SYNC in the high logic state and must be less than V_SYNC in the low logic state. The duty cycle of the external synchronization pulse is not limited, but the minimum on-pulse and the minimum off-pulse widths must be greater than 100 ns. The frequency of the external synchronization pulse must satisfy the following two inequalities.

Equation 8.

For example, an RT resistor is required for typical 350-kHz switching to cover from 263-kHz to 525-kHz clock synchronization without changing the RT resistor.

Figure 8-9 External Clock Synchronization

Drive the SYNC pin through a minimum 1-kΩ resistor if the BIAS pin voltage is less than the SYNC pin voltage in any conditions.