ZHCSEI6 January   2016 LM5140-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High Voltage Start-up Regulator
      2. 8.3.2  VCC Regulator
      3. 8.3.3  Oscillator
      4. 8.3.4  SYNIN and SYNOUT
      5. 8.3.5  Enable
      6. 8.3.6  Power Good
      7. 8.3.7  Output Voltage
      8. 8.3.8  Minimum Output Voltage Adjustment
      9. 8.3.9  Current Sense
      10. 8.3.10 DCR Current Sensing
      11. 8.3.11 Error Amplifier and PWM Comparator
      12. 8.3.12 Slope Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hiccup Mode Current Limiting
      2. 8.4.2 Standby Mode
      3. 8.4.3 Soft-Start
      4. 8.4.4 Diode Emulation
      5. 8.4.5 High and low-side Drivers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Inductor Calculation
        2. 9.2.2.2  Current Sense Resistor
        3. 9.2.2.3  Output Capacitor
        4. 9.2.2.4  Input Filter
        5. 9.2.2.5  EMI Filter Design
        6. 9.2.2.6  MOSFET Selection
        7. 9.2.2.7  Driver Slew Rate Control
        8. 9.2.2.8  Sub-Harmonic Oscillation
        9. 9.2.2.9  Control Loop
        10. 9.2.2.10 Error Amplifier
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Procedure
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

RWG Package
40 Pin VQFN
Top View
LM5140-Q1 po_snvsa02.gif
Connect Exposed Pad on bottom to AGND and PGND on the PCB.

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
SS2 1 I Channel 2 soft-start programming pin. An external capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft-start. Pulling SS pin below 80mV turns-off the channel 2 gate driver outputs, but all the other functions remain active.
COMP2 2 O Output of the channel 2 transconductance error amplifier.
FB2 3 I Feedback input of channel 2. Connect the FB2 pin to VDD for a 5 V output or connect FB2 to ground for a fixed 8V output. A resistive divider from the VOUT2 to the FB2 pin sets the output voltage level between 1.5 V and 15 V. The regulation threshold at the FB2 pin is 1.2 V.
CS2 4 I Channel 2 current sense amplifier input. Make a low current Kelvin connection between this pin and the inductor side of the external current sense resistor.
VOUT2 5 I Output and the current sense amplifier input of channel 2 . Connect this pin to the output side of the channel 2 current sense resistor.
VCCX 6 I Optional input for an external bias supply. If VCCX > 4.5 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. If VCCX is unused, it should be grounded.
PG2 7 O An open collector output which goes low if VOUT2 is outside a specified regulation window.
HOL2 8 O Channel 2 high-side gate driver turn-off output.
HO2 9 O Channel 2 high-side gate driver turn-on output.
SW2 10 I Switching node of the channel 2 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET.
HB2 11 O Channel 2 high-side driver supply for bootstrap gate drive.
LOL2 12 O Channel 2 low-side gate driver turn-off output.
LO2 13 O Channel 2 low-side gate driver turn-on output.
PGND2 14 G Power ground connection pin for low-side NMOS gate driver.
VCC 15 P VCC bias supply pin. Pin 15 and pin 16 must to be connected together on the PCB.
VCC 16 P VCC bias supply pin. Pin 15 and pin 16 must to be connected together on the PCB.
PGND1 17 G Power ground connection pin for low-side NMOS gate driver.
LO1 18 O Channel 1 low-side gate driver turn-on output.
LOL1 19 O Channel 1 low-side gate driver turn-off output.
HB1 20 O Channel 1 high-side driver supply for bootstrap gate drive.
SW1 21 I Switching node of the channel 1 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET.
HO1 22 O Channel 1 high-side gate driver turn-on output
HOL1 23 O Channel 1 high-side gate driver turn-off output.
PG1 24 O An open collector output which goes low if VOUT1 is outside a specified regulation window.
VIN 25 P Supply voltage input source for the VCC regulators.
VOUT1 26 I VOUT1 and current sense amplifier input of channel 1. Connect to the output side of the channel 1 current sense resistor.
CS1 27 I Channel 1 current sense amplifier input. Make a low current Kelvin connection between this pin and the inductor side of the external current sense resistor.
FB1 28 I Feedback input of channel 1. Connect the FB1 pin to VDDA for a 3.3-V output or connect FB1 to ground for a 5-V output. A resistive divider from the VOUT1 to the FB1 pin sets the output voltage level between 1.5 V and 15 V. The regulation threshold at the FB1 pin is 1.2 V.
COMP1 29 O Output of the channel 1 transconductance error amplifier.
SS1 30 I Channel 2 soft-start programming pin. An external capacitor and an internal 20μA current source set the ramp rate of the internal error amplifier reference during soft-start. Pulling SS pin below 80mV turns-off the channel 1 gate driver outputs, but the all the other function remain active.
EN1 31 I An active high logic input enables channel 1.
RES 32 O Restart timer pin. An external capacitor configures the hiccup mode current limiting. The capacitor at the RES pin determines the time the controller will remain off before automatically restarting in hiccup mode. The two regulator channels operate independently. One channel may operate in normal mode while the other is in hiccup mode overload protection. The hiccup mode commences when either channel experiences 512 consecutive PWM cycles with cycle-by-cycle current limiting. Connect the RES pin to VDD during power up to disable hiccup mode protection.
DEMB 33 I Diode Emulation pin. If the DEMB pin is grounded, diode emulation is enabled. If it is connected to VDDA the LM5140-Q1 operates in FPWM mode with continuous conduction at light loads.
ILSET 34 I Current Limit Threshold pin. Connecting the ILSET pin to VDDA sets the current limit threshold to 73 mV for channel 1 and channel 2.
Connecting the ILSET pin to GND sets the current limit thresholds to 48 mV.
AGND 35 G Analog ground connection. Ground return for the internal voltage reference and analog circuits.
VDDA 36 P Internal analog bias regulator output. Connect a capacitor from the VDDA pin the AGND.
OSC 37 I Frequency selection pin. Connecting the OSC pin to VDDA selects the default oscillator frequency of 2.2 MHz. Connecting the OSC pin to ground sets frequency to 440 kHz.
SYNIN 38 I Sync input pin. The internal oscillator can be synchronized to an external clock. If the synchronization feature is not used, the SYNIN pin should be connected to AGND.
SYNOUT 39 O Sync output pin. The TTL level output signal is 180º out of phase with the HO1 gate drive of channel 1.
EN2 40 I An active high logic input enables channel 2.
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