7.3.17 High- and Low-Side Drivers

The LM5141-Q1 contains N-channel MOSFET gate drivers and an associated high-side level shifter to drive the external N-channel MOSFETs. The high-side gate driver works in conjunction with an external bootstrap diode D_BST, and bootstrap capacitor C_BST (refer to Figure 27). During the on-time of the low-side MOSFET, the SW pin voltage is approximately 0 V, and C_BST is charged from VCC through the D_BST. A 0.1-μF or larger ceramic capacitor, connected with short traces between the HB and SW pin is recommended.

The LO and HO outputs are controlled with an adaptive dead-time methodology which ensures that both outputs (HO and LO) are never enabled at the same time, preventing cross conduction. When the controller commands LO to be enabled, the adaptive dead-time logic first disables HO and waits for the HO-SW voltage to drop below 2.5 V typical. LO is then enabled after a small delay (HO falling to LO rising delay). Similarly, the HO turn-on is delayed until the LO voltage has dropped below 2.5 V. HO is then enabled after a small delay (LO falling to HO rising delay). This technique ensures adequate dead-time for any size N-channel MOSFET device or parallel MOSFET configurations. Caution is advised when adding series gate resistors, as this may decrease the effective dead-time. Each of the high and low-side drivers have independent driver source and sink output pins. This allows the user to adjust drive strength to optimize the switching losses for maximum efficiency and to control the slew rate for reduced EMI. The selected N-channel high-side MOSFET determines the appropriate boost capacitance values C_BST in Figure 27 according toEquation 14.

Equation 14.

where

• Q_G is the total gate charge of the high-side MOSFET
• ΔV_BST is the voltage variation allowed on the high-side MOSFET driver after turnon

Choose ΔV_BST such that the available gate-drive voltage is not significantly degraded when determining C_BST. A typical range of ΔV_BST is 100 mV to 300 mV. The bootstrap capacitor should be a low-ESR ceramic capacitor. A minimum value of 0.1 μF to 0.47 μF is best in most cases. The gate threshold of the high-side and low-side MOSFETs should be a logic level variety appropriate for 5-V gate drive.

Figure 27. Drivers