ZHCSIY8C October   2018  – June 2021 LM5143-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN)
      2. 8.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 8.3.3  Enable (EN1, EN2)
      4. 8.3.4  Power Good Monitor (PG1, PG2)
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Clock Synchronization (DEMB)
      7. 8.3.7  Synchronization Out (SYNCOUT)
      8. 8.3.8  Spread Spectrum Frequency Modulation (DITH)
      9. 8.3.9  Configurable Soft Start (SS1, SS2)
      10. 8.3.10 Output Voltage Setpoint (FB1, FB2)
      11. 8.3.11 Minimum Controllable On-Time
      12. 8.3.12 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
      13. 8.3.13 Slope Compensation
      14. 8.3.14 Inductor Current Sense (CS1, VOUT1, CS2, VOUT2)
        1. 8.3.14.1 Shunt Current Sensing
        2. 8.3.14.2 Inductor DCR Current Sensing
      15. 8.3.15 Hiccup Mode Current Limiting (RES)
      16. 8.3.16 High-Side and Low-Side Gate Drivers (HO1/2, LO1/2, HOL1/2, LOL1/2)
      17. 8.3.17 Output Configurations (MODE, FB2)
        1. 8.3.17.1 Independent Dual-Output Operation
        2. 8.3.17.2 Single-Output Interleaved Operation
        3. 8.3.17.3 Single-Output Multiphase Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Standby Modes
      2. 8.4.2 Diode Emulation Mode
      3. 8.4.3 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 Power MOSFETs
        5. 9.1.1.5 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High Efficiency, Dual-Output Buck Regulator for Automotive Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 9.2.1.2.3 Inductor Calculation
          4. 9.2.1.2.4 Current-Sense Resistance
          5. 9.2.1.2.5 Output Capacitors
          6. 9.2.1.2.6 Input Capacitors
          7. 9.2.1.2.7 Compensation Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Two-Phase, Single-Output Buck Regulator for Automotive ADAS Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedures
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate-Drive Layout
      3. 11.1.3 PWM Controller Layout
      4. 11.1.4 Thermal Design and Layout
      5. 11.1.5 Ground Plane Design
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 12.1.2 Development Support
      3. 12.1.3 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. 12.2.1.1 PCB Layout Resources
        2. 12.2.1.2 Thermal Design Resources
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

GUID-14A4491E-C7C7-44B3-8355-F9280B66B781-low.gif
Connect Exposed Pad on the bottom to AGND and PGND on the PCB.
Figure 6-1 RWG Package40-Pin VQFNP with Wettable Flanks(Top View)
Table 6-1 Pin Functions
PIN I/O (1) DESCRIPTION
NO. NAME
1 SS2 I Channel 2 soft-start programming pin. An external ceramic capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft start. Pulling SS2 below 150 mV turns off the channel 2 gate driver outputs, but all the other functions remain active.
2 COMP2 O Output of the channel 2 transconductance error amplifier. COMP2 is high impedance in interleave or slave mode.
3 FB2 I Feedback input of channel 2. Connect FB2 to VDDA for a 3.3-V output or connect FB2 to AGND for a fixed 5-V output. A resistive divider from VOUT2 to FB2 sets the output voltage level between 0.6 V and 55 V. The regulation threshold at FB2 is 0.6 V.
4 CS2 I Channel 2 current sense amplifier input. Connect CS2 to the inductor side of the external current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low-current Kelvin connection.
5 VOUT2 I Output voltage sense and the current sense amplifier input of channel 2. Connect VOUT2 to the output side of the channel 2 current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used).
6 VCCX P Optional input for an external bias supply. If VVCCX > 4.3 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. Connect a ceramic capacitor between VCCX and PGND.
7 PG2 O An open-collector output which goes low if VOUT2 is outside a specified regulation window.
8 HOL2 O Channel 2 high-side gate driver turnoff output.
9 HO2 O Channel 2 high-side gate driver turnon output.
10 SW2 P Switching node of the channel 2 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
11 HB2 P Channel 2 high-side driver supply for bootstrap gate drive.
12 LOL2 O Channel 2 low-side gate driver turnoff output.
13 LO2 O Channel 2 low-side gate driver turnon output.
14 PGND2 G Power ground connection pin for low-side NMOS gate driver.
15, 16 VCC P VCC bias supply pin. Pins 15 and 16 must to be connected together on the PCB. Connect ceramic capacitors between VCC and PGND1 and between VCC and PGND2.
17 PGND1 G Power ground connection pin for low-side NMOS gate driver.
18 LO1 O Channel 1 low-side gate driver turnon output.
19 LOL1 O Channel 1 low-side gate driver turnoff output.
20 HB1 P Channel 1 high-side driver supply for bootstrap gate drive.
21 SW1 P Switching node of the channel 1 buck regulator. Connect to the channel 1 bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET.
22 HO1 O Channel 1 high-side gate driver turnon output.
23 HOL1 O Channel 1 high-side gate driver turnoff output.
24 PG1 O An open-collector output that goes low if VOUT1 is outside a specified regulation window.
25 VIN P Supply voltage input source for the VCC regulators.
26 VOUT1 I Output voltage sense and the current sense amplifier input of channel 1. Connect VOUT1 to the output side of the channel 1 current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used).
27 CS1 I Channel 1 current sense amplifier input. Connect CS1 to the inductor side of the external current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low-current Kelvin connection.
28 FB1 I Feedback input of channel 1. Connect the FB1 pin to VDDA for a 3.3-V output or connect FB1 to AGND for a 5-V output. A resistive divider from VOUT1 to FB1 sets the output voltage level between 0.6 V and 55 V. The regulation threshold at FB1 is 0.6 V.
29 COMP1 O Output of the channel 1 transconductance error amplifier (EA).
30 SS1 I Channel 1 soft-start programming pin. An external capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft start. Pulling the SS1 voltage below 150 mV turns off the channel 1 gate driver outputs, but the all the other functions remain active.
31 EN1 I An active high input (VEN1 > 2 V) enables Output 1. If Outputs 1 and 2 are disabled, the LM5143-Q1 is in shutdown mode unless a SYNC signal is present at DEMB. EN1 must never be floating.
32 RES O Restart timer pin. An external capacitor configures the hiccup-mode current limiting. A capacitor at the RES pin determines the time the controller remains off before automatically restarting in hiccup mode. The two regulator channels operate independently. One channel can operate in normal mode while the other is in hiccup-mode overload protection. The hiccup mode commences when either channel experiences 512 consecutive PWM cycles with cycle-by-cycle current limiting. Connect RES to VDDA during power-up to disable hiccup-mode protection.
33 DEMB I Diode Emulation pin. Connect DEMB to AGND to enable diode emulation mode. Connect DEMB to VDDA to operate the LM5143-Q1 in forced PWM (FPWM) mode with continuous conduction at light loads. DEMB can also be used as a synchronization input to synchronize the internal oscillator to an external clock.
34 MODE I Connect MODE to AGND or VDDA for dual-output or interleaved single-output operation, respectively. This also configures the LM5143-Q1 with an EA transconductance of 1200 µS. Connecting a 10-kΩ resistor between MODE and AGND sets the LM5143-Q1 for dual-output operation with an ultra-low IQ mode and an EA transconductance of 60 µS.
35 AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits.
36 VDDA O Internal analog bias regulator output. Connect a ceramic decoupling capacitor from VDDA to AGND.
37 RT I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100 kHz and 2.2 MHz.
38 DITH I A capacitor connected between the DITH pin and AGND is charged and discharged with a 20-µA current source. If dithering is enabled, the voltage on the DITH pin ramps up and down modulating the oscillator frequency between –5% and +5% of the internal oscillator. Connecting DITH to VDDA during power-up disables the dither feature. DITH is ignored if an external synchronization clock is used.
39 SYNCOUT O SYNCOUT is a logic level signal with a rising edge approximately 90° lagging HO2 (or 90° leading HO1). When the SYNCOUT signal is used to synchronize a second LM5143-Q1 controller, all phases are 90° out of phase.
40 EN2 I An active high input (VEN2 > 2 V) enables Output 2. If Outputs 1 and 2 are disabled, the LM5143-Q1 is in shutdown mode unless a SYNC signal is present on DEMB. EN2 must never be floating.
(1) P = Power, G = Ground, I = Input, O = Output
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