The SS/TRK pin also doubles as a tracking pin when master-slave power-supply tracking is required. This tracking is achieved by simply dividing down the output voltage of the master with a simple resistor network. Coincident, ratiometric, and offset tracking modes are possible.

If an external voltage source is connected to the SS/TRK pin, the external soft-start capability of the LM5146 is effectively disabled. The regulated output voltage level is reached when the SS/TRK pin reaches the 0.8-V reference voltage level. It is the responsibility of the system designer to determine if an external soft-start capacitor is required to keep the device from entering current limit during a start-up event. Likewise, the system designer must also be aware of how fast the input supply ramps if the tracking feature is enabled.

Figure 8-6 Typical Output Voltage Tracking and PGOOD Waveforms

Figure 8-6 shows a triangular voltage signal directly driving SS/TRK and the corresponding output voltage tracking response. Nominal output voltage here is 5 V, with oscilloscope channel scaling chosen such that the waveforms overlap during tracking. As expected, the PGOOD flag transitions at thresholds of 94% (rising) and 92% (falling) of the nominal output voltage setpoint.

Two practical tracking configurations, ratiometric and coincident, are shown in Figure 8-7. The most common application is coincident tracking, used in core versus I/O voltage tracking in DSP and FPGA implementations. Coincident tracking forces the master and slave channels to have the same output voltage ramp rate until the slave output reaches its regulated setpoint. Conversely, ratiometric tracking sets the output voltage of the slave to a fraction of the output voltage of the master during start-up.

For coincident tracking, connect the SS/TRK input of the slave regulator to a resistor divider from the output voltage of the master that is the same as the divider used on the FB pin of the slave. In other words, simply select R_TRK3 = R_FB3 and R_TRK4 = R_FB4 as shown in Figure 8-7. As the master voltage rises, the slave voltage rises identically (aside from the 80-mV offset from SS/TRK to FB when V_FB is below 0.8 V). Eventually, the slave voltage reaches its regulation voltage, at which point the internal reference takes over the regulation while the SS/TRK input continues to 115 mV above FB, and no longer controls the output voltage.

In all cases, to ensure that the output voltage accuracy is not compromised by the SS/TRK voltage being too close to the 0.8-V reference voltage, the final value of the SS/TRK voltage of the slave should be at least 100 mV above FB.