The LM5148-Q1 contains gate drivers and an associated high-side level shifter to drive the external N-channel power MOSFETs. The high-side gate driver works in conjunction with an internal bootstrap diode D_BOOT and bootstrap capacitor C_BOOT. During the conduction interval of the low-side MOSFET, the SW voltage is approximately 0 V and CBOOT charges from VCC through the internal D_BOOT. TI recommends a 0.1-μF ceramic capacitor connected with short traces between the CBOOT and SW pins.

The LO and HO outputs are controlled with an adaptive dead-time methodology so that both outputs (HO and LO) are never on at the same time, preventing cross conduction. Before the LO driver output is allowed to turn on, the adaptive dead-time logic first disables HO and waits for the HO voltage to drop below 2 V typical. LO is allowed to turn on after a small delay (HO fall to LO rising delay). Similarly, the HO turn-on is delayed until the LO voltage has dropped below 2 V. This technique ensures adequate dead-time for any size N-channel power MOSFET implementations, including parallel MOSFET configurations.

Caution is advised when adding series gate resistors, as this can impact the effective dead-time. The selected high-side MOSFET determines the appropriate bootstrap capacitance value C_BOOT in accordance with Equation 12.

Equation 12.

where

• Q_G is the total gate charge of the high-side MOSFET at the applicable gate drive voltage.
• ΔV_CBOOT is the voltage variation of the high-side MOSFET driver after turn-on.

To determine C_BOOT, choose ΔV_CBOOT such that the available gate drive voltage is not significantly impacted. An acceptable range of ΔV_CBOOT is 100 mV to 300 mV. The bootstrap capacitor must be a low-ESR ceramic capacitor, typically 0.1 µF. Use high-side and low-side MOSFETs with logic-level gate threshold voltages.