ZHCSPX4A February   2022  – April 2022 LM5152-Q1 , LM51521-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Enable/Disable (EN, VH Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 9.3.4  Line Undervoltage Lockout (UVLO Pin)
      5. 9.3.5  Fast Restart Using VCC HOLD (VH Pin)
      6. 9.3.6  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      7. 9.3.7  Overvoltage Protection (VOUT Pin)
      8. 9.3.8  Boost Status Indicator (STATUS Pin)
      9. 9.3.9  Dynamically Programmable Switching Frequency (RT)
      10. 9.3.10 External Clock Synchronization (SYNC Pin)
      11. 9.3.11 Programmable Spread Spectrum (DITHER Pin)
      12. 9.3.12 Programmable Soft Start (SS Pin)
      13. 9.3.13 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      14. 9.3.14 Current Sensing and Slope Compensation (CSP, CSN Pin)
      15. 9.3.15 Constant Peak Current Limit (CSP, CSN Pin)
      16. 9.3.16 Maximum Duty Cycle and Minimum Controllable On-Time Limits
      17. 9.3.17 Deep Sleep Mode and Bypass Operation (HO, CP Pin)
      18. 9.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      19. 9.3.19 Thermal Shutdown Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Status
        1. 9.4.1.1 Shutdown Mode
        2. 9.4.1.2 Configuration Mode
        3. 9.4.1.3 Active Mode
        4. 9.4.1.4 Sleep Mode
        5. 9.4.1.5 Deep Sleep Mode
      2. 9.4.2 Light Load Switching Mode
        1. 9.4.2.1 Forced PWM (FPWM) Mode
        2. 9.4.2.2 Diode Emulation (DE) Mode
        3. 9.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 9.4.2.4 Skip Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application Ideas
      3. 10.2.3 Application Curves
    3. 10.3 System Example
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

Device Enable/Disable (EN, VH Pin)

The device shuts down when EN is less than the EN threshold (VEN) and VH is less than the SYNC threshold (VSYNC). The device is enabled when EN is greater than VEN or VH is greater than VSYNC. The VH pin provides a 40-μs internal delay before the device shuts down.

During shutdown, a 33-kΩ internal pulldown resistor on the EN pin is connected to GND to prevent a false turn-on when the pin is floating. Once EN goes above the EN threshold (VEN), the 33-kΩ resistor is disconnected and the IUVLO-HYS current source is enabled to provide the UVLO functionality. The IUVLO-HYS current is designed to avoid chatter around the EN threshold voltage.

GUID-20200807-CA0I-S7S4-BLJ8-01L3M4MCD6GC-low.gif Figure 9-1 EN/UVLO Circuit