The performance of switching converters heavily depends on the quality of the PCB layout. The following guidelines will help users design a PCB with the best power conversion performance, thermal performance, and minimize generation of unwanted EMI.

• Place C_VCC, C_BIAS, C_HB, and C_VOUT as close to the device. Make direct connections to the pins.
• Place Q_H, Q_L, and C_OUT. Make the switching loop (C_OUT to Q_H to Q_L to C_OUT) as small as possible. A small size ceramic capacitor helps to minimize the loop length. Leave a copper area near the drain connection of Q_H for a thermal dissipation.
• Place L_M, R_S, and C_IN. Make the loop (C_IN to R_S to L_M to C_IN) as small as possible. A small size ceramic capacitor helps to minimize the loop length.
• Connect R_S to CSP-CSN. The CSP-CSN traces must be routed in parallel and surrounded by ground.
• Connect VOUT, HO, and SW. These traces must be routed in parallel using a short, low inductance path. VOUT must be directly connected the drain connection of Q_H. SW must be directly connected to the source connection of Q_H
• Connect LO and PGND. The LO-PGND traces must be routed in parallel using a short, low inductance path. PGND must be directly connected the source connection of Q_L.
• Place R_COMP, C_COMP, C_SS, C_VREF, R_VREFT, R_VREFB, R_T, and R_UVLOB as close to the device, and connect to a common analog ground plane.
• Connect the power ground plane (the source connection of the Q_L) to EP through PGND. Connect the common analog ground plane to EP through AGND. PGND and AGND must be connected underneath the device.
• Add several vias under EP to help conduct heat away from the device. Connect the vias to a large analog ground plane on the bottom layer.
• Do not connect C_OUT and C_IN grounds underneath the device and through the large analog ground plane that is connected to EP.