ZHCSOB0A july 2021 – august 2023 LM5157
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
- 8.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
- 8.3.3 Soft Start (SS Pin)
- 8.3.4 Switching Frequency (RT Pin)
- 8.3.5 Dual Random Spread Spectrum – DRSS (MODE Pin)
- 8.3.6 Clock Synchronization (UVLO/SYNC/EN Pin)
- 8.3.7 Current Sense and Slope Compensation
- 8.3.8 Current Limit and Minimum On Time
- 8.3.9 Feedback and Error Amplifier (FB, COMP Pin)
- 8.3.10 Power-Good Indicator (PGOOD Pin)
- 8.3.11 Hiccup Mode Overload Protection (MODE Pin)
- 8.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
- 8.3.13 Internal MOSFET (SW Pin)
- 8.3.14 Overvoltage Protection (OVP)
- 8.3.15 Thermal Shutdown (TSD)
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
The practical duty cycle is greater than the estimated due to voltage drops across the MOSFET and sense resistor. The estimated duty cycle is calculated as shown in Equation 10.
When designing boost converters, the maximum required duty cycle must be reviewed at the minimum supply voltage. The minimum input supply voltage that can achieve the target output voltage is limited by the maximum duty cycle limit, and it can be estimated as follows:
where
- ISUPPLY(MAX) is the maximum input current
- RDCR is the DC resistance of the inductor
The minimum input supply voltage can be further decreased by supplying fSYNC, which is less than fRT. Practical DMAX is DMAX1 or DMAX2, whichever is lower.