The device senses switch current, which flows into the SW pin and provides a fixed internal slope compensation ramp, which helps prevent subharmonic oscillation at high duty cycle. The internal slope compensation ramp is added to the sensed switch current for the PWM operation. But, no slope compensation ramp is added to the sensed inductor current for the current limit operation to provide an accurate peak current limit over the input supply voltage (see Figure 9-17).

Figure 9-17 Current Sensing and Slope Compensation

Figure 9-18 Current Sensing and Slope Compensation (a) at PWM Comparator Inputs

Figure 9-19 Current Sensing (b) at Current Limit Comparator Inputs

Use Equation 6 to calculate the value of the peak slope voltage (V_SLOPE).

Equation 6.

where

• f_SYNC is f_RT if clock synchronization is not used.

According to peak current mode control theory, the slope of the compensation ramp must be greater than half of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the minimum amount of slope compensation in boost topology must satisfy the following inequality:

Equation 7.

where

• V_F is a forward voltage drop of D1, the external diode.

Typically 82% of the sensed inductor current falling slope is known as an optimal amount of the slope compensation. By increasing the margin to 1.6, the amount of slope compensation becomes close to the optimal amount.

If clock synchronization is not used, the f_SW frequency equals the f_RT frequency. If clock synchronization is used, the f_SW frequency equals the f_SYNC frequency.