ZHCSFE2A August 2016 – November 2017 LM5161-Q1
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | HTSSOP | ||
AGND | 1 | - | Analog Ground. Ground connection of internal control circuits. |
PGND | 2 | - | Power Ground. Ground connection of the internal synchronous rectifier FET. |
VIN | 3 | I | Input supply connection. Operating input range is 4.5-V to 100-V. |
EN/UVLO | 4 | I | Precision enable. Input pin of undervoltage lockout (UVLO) comparator. |
RON | 5 | I | On-time programming pin. A resistor between this pin and VIN sets the switch ON-time as a function of input voltage. |
SS | 6 | I | Softstart. Connect a capacitor from SS to AGND to control output rise time and limit overshoot. |
FPWM | 8 | I | Forced PWM logic input pin. Connect to AGND for discontinuous conduction mode (DCM) with light loads. Connect to VCC for continuous conduction mode (CCM) at all loads and Fly-Buck configuration. |
FB | 9 | I | Feedback input of voltage regulation comparator. |
VCC | 10 | O | Internal high voltage start-up regulator bypass capacitor pin. |
BST | 11 | I | Bootstrap capacitor pin. Connect a capacitor between BST and SW to bias gate driver of high-side buck FET. |
SW | 12,13 | O | Switch node. Source connection of high side buck FET and drain connection of low-side synchronous rectifier FET. |
NC | 7,14 | No Connection. | |
EP | - | Exposed Pad. Connect to AGND and printed-circuit board ground plane to improve power dissipation. |